Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/630,248 filed on April 09, 2024.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-10) in the reply filed on 07/20/2025 is acknowledged.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2023/0209826 to Yook et al. (Yook).
Regarding independent claim 1, Yook discloses a semiconductor device (Fig. 11), comprising:
a substrate (Fig. 11: 100) having a pair of second conductive lines (Fig. 11: SCP2 and ¶0068 states that second source conductive patterns SCP2 are sequentially stacked, and Fig. 11 shows multiple SCP2 structures. Under BRI, selecting two adjacent SCP2 conductive patterns as the claimed “pair” is a reasonable interpretation) thereon;
a first conductive line (SCP1) extending between the pair of second conductive lines (SCP2) and the substrate (100) (¶0068 states SCP1 and SCP2 are source conductive patterns, and Fig. 11 shows SCP1 located between neighboring SCP2 structures);
a contact plug (Fig. 11: CP1) that extends between the pair of second conductive lines (SCP2) and is electrically connected to the first conductive line (SCP1) (¶0074 expressly identifies CP1 as a contact plug, and Fig. 11 shows CP1 positioned between adjacent SCP2 structures);
a gate electrode (EL) on the contact plug (CP1) (Figure 11 shows gate electrode EL adjacent to and directly contacting contact plug CP1. Under the broadest reasonable interpretation, the claimed “on the contact plug” encompasses direct sidewall contact because the claim does not require that the gate electrode be located on an upper surface of the contact plug, nor does the specification define “on” more narrowly.);
first and second semiconductor patterns (Fig. 11: VSP and ¶0071-0074) extending on first and second ones of the pair of second conductive lines (SCP2) (VSP contacting/being formed relative to SCP2), respectively;
a gate insulating pattern (Fig. 11: VI or ILDa or ILDb) extending between each of the first and second semiconductive patterns (VSP) and the gate electrode (EL) (Figure 11 and ¶0071 - 0074 disclose a plurality of vertical semiconductor patterns (VSP). The insulating pattern VI is disposed between the gate electrodes EL and the respective vertical semiconductor patterns VSP. Because a plurality of VSP structures are provided, the insulating pattern VI extends between each respective semiconductor pattern VSP and the corresponding gate electrode EL, as claimed); and
first and second conductive patterns (Fig. 11: PAD) extending on the first and second semiconductor patterns (VSP), respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2023/0209826 to Yook et al. (Yook) in view of US Pat # 6,689,660 to Noble et al. (Noble).
Regarding claim 4, Yook teaches a semiconductor device including a substrate, conductive lines, contact plug, gate electrode, semiconductor patterns, gate insulating pattern, and conductive patterns (see, e.g., Fig. 11 and ¶60, 67–74 and the rejection of claim 1 above).
However, the Yook does not expressly disclose wherein the first conductive line is configured as a word line, wherein the pair of second conductive lines are configured as a pair of bit lines, and wherein the gate electrode is configured as the gate electrode of a first access transistor within a first DRAM cell and as the gate electrode of a second access transistor within a second DRAM cell, as recited.
Noble teaches a DRAM memory array (Figs. 1-3) including word lines (206-208), bit lines (202 and 204), and access transistors (130), wherein the word lines function as gate electrodes for the access transistors of adjacent DRAM memory cells (see, e.g., Figs. 1-3 and col. 4, lines 8-14).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to configure the conductive line arrangement of the semiconductor memory device of the Yook according to the conventional DRAM architecture taught by the Noble, wherein conductive lines are configured as word lines and bit lines and the word lines serve as gate electrodes of access transistors of adjacent DRAM cells that results a high density semiconductor memory array having an improved topography and which achieves the low noise benefits of a folded bit line architecture (col.2, lines 16-20), because Yook and Noble are directed to semiconductor DRAM memory devices and such modification merely employs a well-known memory array configuration to obtain predictable results, including conventional DRAM addressing and memory cell operation.
Regarding claim 5, Yook teaches a semiconductor device including a substrate, conductive lines, contact plug, gate electrode, semiconductor patterns, gate insulating pattern, and conductive patterns (see, e.g., Fig. 11 and ¶60, 67–74 and the rejection of claim 1 above).
However, the Yook does not expressly disclose wherein the first conductive line extends across a surface of the substrate in a first direction; wherein the pair of second conductive lines extend across the surface of the substrate in a second direction; and wherein the first direction is perpendicular to the second direction.
Noble teaches (Fig. 2) that the word lines (206-208) extend in a first direction, the bit lines (202 and 204) extend in a second direction, and the first and second directions are perpendicular to each other, as shown in Figs. 1-3.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to arrange the conductive lines of the modified semiconductor memory device such that the first conductive line extends in a first direction and the pair of second conductive lines extend in a second direction perpendicular to the first direction that results a high density semiconductor memory array having an improved topography and which achieves the low noise benefits of a folded bit line architecture (col.2, lines 16-20) because this is the conventional layout of DRAM memory arrays and provides predictable memory addressing and access.
Allowable Subject Matter
Claims 2-3 and 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites:
“wherein the first and second conductive patterns (PAD) are electrically connected to a capacitor electrode of a first capacitor and a capacitor electrode of a second capacitor, respectively; wherein the first conductive line is configured as a word line; wherein the pair of second conductive lines are configured as a pair of bit lines; and wherein the gate electrode is configured as a gate electrode of a first access transistor within a first DRAM cell and as a gate electrode of a second access transistor within a second DRAM cell.”
Each of the above recitations, interpreted in combination with all other limitations of the claim and all limitations of any claims they depend from, is not taught or rendered obvious by the prior art of record and are indicated as allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2023/0025248 to Son et al., US Pub # 2023/0206976 to Lee et al., US Pub # 2022/0199767 to Lee et al., US Pat # 6,849,889 to Jang and US Pub # 2021/0327805 to Lee et al.
Son discloses a semiconductor device (Fig. 6), comprising vertical channel structures VS include a data storage pattern DSP, which is adjacent to the stack structure ST or covers an inner side surface of each of the vertical channel holes CH, a vertical semiconductor pattern VSP, which is provided to conformally cover an inner side surface of the data storage pattern DSP, a gapfill insulating pattern VI, which is provided to fill an internal space delimited by the vertical semiconductor pattern VSP, and a conductive pad, which is provided in a space delimited by the gapfill insulating pattern VI and the data storage pattern DSP, the vertical semiconductor pattern VSP provided between the data storage pattern DSP and the gapfill insulating pattern VI, the vertical semiconductor pattern VSP shaped like a bottom-closed pipe or macaroni, the vertical semiconductor pattern VSP is in contact with a portion of the source structure SC, the vertical semiconductor pattern VSP formed of or include poly silicon.
However, Son does not teach a contact plug that extends between the pair of second conductive lines and is electrically connected to the first conductive line, first and second semiconductor patterns extending on first and second ones of the pair of second conductive lines, respectively and first and second conductive patterns extending on the first and second semiconductor patterns, respectively.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
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