Attorney’s Docket Number: 8947-001985-US
Filing Date: 04/09/2024
Claimed Priority Date: 05/23/2023 (KR10-2023-0137071)
Applicants: Park et al.
Examiner: Aneesa Baig
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In [0029], “the tap cell.” should be corrected to – the tab cell.—
Drawings
The drawings of Figure 5B are objected to under 37 CFR 1.83(a) because they fail to show features as described in the specification.
Fig 5B is not A-A’ X section, rather of line B-B’ , as described in Par [0011]
VI1 connecting to second metal layer M2, should be VI2, as described in Par [0086]
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 rejected under 35 U.S.C. 102 (a)(2) as anticipated by OH et al (US 20240395807 A1 Hereinafter OH).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 102 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding Claim 1, OH (e.g., Fig 1-18and corresponding paragraphs) shows all aspects of the instant invention, including, semiconductor device, comprising:
an active pattern on a substrate (AP1, AP2 etc on substrate 100, 100p), defined by a trench, and extending in a first direction (Fig 19B shows the trench);
a device isolation layer filling the trench ( Fig 5 field insulating film 105), the substrate comprising a first surface in contact with a bottom surface of the device isolation layer and a second surface opposite to the first surface;
a gate electrode (gate electrodes 120) extending in a second direction and cross the active pattern, the second direction crossing the first direction;
a first division structure spaced apart from the gate electrode in the first direction and extending in the second direction (Fig 5 active cutting structure ASS); and
a power delivery network layer on the second surface of the substrate (power rail PR),
wherein the first division structure penetrates the device isolation layer (Fig 21B and Fig 5, ASS penetrates 105 [0108]), and a bottom surface of the first division structure is coplanar with the second surface of the substrate
Regarding Claim 2, OH shows the first division structure comprises a material having an etch selectivity with respect to the substrate ([0111]),
Regarding Claim 3, OH shows the following :
a source/drain pattern on the active pattern (first source/drain pattern 150);
a first metal layer on the source/drain pattern, the first metal layer comprising a power line (first source/drain contact 170, a first via plug 195) ; and
a penetration via (VCT, contacting the PR and 195, Fig 4) penetrating the device isolation layer and the substrate and connecting the power line to the power delivery network layer, wherein a bottom surface of the penetration via is coplanar with the bottom surface of the first division structure.
Regarding Claim 6, OH shows in (Fig 5) the first division structure (ASS) is in physical contact with the PDN (PR).
Regarding Claim 8, OH shows
a channel pattern on the active pattern,
wherein the channel pattern comprises a plurality of semiconductor patterns (SP1 and Sp2, Figs 3 and 6), which are stacked to be spaced apart from each other, and the gate electrode encloses side surfaces, a top surface, and a bottom surface of each of the semiconductor pattern (Gate electrode 120 encloses the SP patterns).
Regarding Claim 10, OH shows a semiconductor device, comprising:
an active pattern on a substrate, defined by a trench, and extending in a first direction (AP1, AP2 etc on substrate 100, 100p),
a device isolation layer filling the trench; a source/drain pattern on the active pattern (105);
a gate electrode extending in a second direction and cross the active pattern, the second direction crossing the first direction (120);
a first division structure spaced apart from the gate electrode in the first direction and extending in the second direction (Fig 5 active cutting structure ASS)
a power delivery network layer on a bottom surface of the substrate (power rail PR);
a first metal layer on the source/drain pattern, the first metal layer comprising a power line; and (first source/drain contact 170, a first via plug 195)
a penetration via vertically penetrating the substrate and the device isolation layer and connecting the power line to the power delivery network layer (VCT, contacting the PR and 195, Fig 4)
wherein the penetration via is at a side of the division structure and is spaced apart from the division structure, and (Fig 5)
a bottom surface of the division structure is coplanar with a bottom surface of the penetration via (bottom of VCT is coplanar with the ASS structure)
Regarding Claim 11, See comments from Claim 2, as they would be considered repeated here.
Regarding Claim 13, See comments from Claim 6, as they would be considered repeated here.
Regarding Claim 20, See comments from Claim 2, as they would be considered repeated here.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over OH.
Regarding Claim 7, OH appears to show that a vertical length of a portion of the first division structure in the device isolation layer (105) is larger than a vertical length of a portion of the first division structure in the substrate (Fig 5) .
Additionally, with regards to the particular ratio of surface dimensions claimed, it is also noted that the specification fails to provide teachings about the criticality of having the length of the column in the isolation layer to be larger and the courts have held that differences in (lengths, widths) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed ratio, and since OH teaches an arrangement of (widths) known in the art, it would have been obvious to one of ordinary skill in the art to use these (width ratio values) in the device of OH.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed dimensions ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions ratios or upon another variable recited in a claim, the applicant must show that the chosen ratios are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Claims 9, 14 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of Lee (KR 20130066198 A, hereinafter Lee ).
Regarding Claim 9, while OH shows a substrate with a planar surface, it fails to show a substrate with a curved surface or a convex surface.
Lee (Fig 20-22, [0039]), on the other hand and in a related field of substrates in semiconductor devices, teaches having a curved surface of the substrate to allow for adding tensile stress to the region. This in turn results in better electron mobility. Further the electron mobility can be controlled by adjusting the curvature of the surface of the substrate.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a curved bottom surface of the substrate in the device of OH, as taught by Lee, to improve electron mobility.
Regarding Claim 14, See comments from Claim 9, as they would be considered repeated here.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of Chen (US 20090269905 A1, hereinafter Chen ).
Regarding Claim 15, OH appears to show a division structure in a column shape that may be tapered, however, it is silent about specifically a width decreasing in a vertical direction.
Chen, on the other hand and in a related field of vias through silicon, teaches a via that is preferably tapered shape, because a via with a tapered profile is inherent to the etch process and is able to reduce voids in filling. Further, tapered via may, reduce undercuts, and improved sidewall coverage of filling layers.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have tapered vias in the device of OH to improve void-free filling of the vias.
Regarding Claim 16, OH shows a semiconductor device, comprising:
an active pattern on a substrate and extending in a first direction (AP1, AP2 etc on substrate 100, 100p);
a device isolation layer defining the active pattern (105);
a channel pattern and a source/drain pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns stacked to be spaced apart from each other (Channel patterns formed from SP1 and SP2 patterns);
a gate electrode on the channel pattern and extending in a second direction crossing the first direction, the gate electrode comprising an inner electrode interposed between adjacent ones of the semiconductor patterns (Gate electrode 120 encloses the SP patterns).;
a gate insulating layer interposed between the gate electrode and the channel pattern gate insulating film 130;
an inner spacer between the inner electrode and the source/drain pattern (gate spacer 140 may include an outer spacer 141 and an inner spacer 142);
a gate spacer on a side surface of the gate electrode (e.g., Fig 14 [0176] gate spacer 140 may include an outer spacer 141 and an inner spacer 142. The inner spacer 142);
a gate capping pattern on a top surface of the gate electrode (gate capping films 145);
a gate cutting pattern penetrating the gate electrode (GSS);
an interlayer insulating layer on the gate capping pattern and the gate cutting pattern (interlayer insulating film 192);
an active contact penetrating the interlayer insulating layer and electrically connected to the source/drain pattern (first via plug 195);
a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode (gate contact 180,);
a first metal layer on the interlayer insulating layer, the first metal layer comprising a first upper interconnection line electrically connected to the active contact ;
a second metal layer on the first metal layer, the second metal layer comprising a second upper interconnection line electrically connected to the first metal layer (Gate contact 180 is illustrated as including a plurality of conductive films.);
a power delivery network layer on a bottom surface of the substrate, the power delivery network layer comprising a lower interconnection line (PR power rail);
a penetration via penetrating the device isolation layer and the substrate and vertically connecting the first upper interconnection line of the first metal layer to the lower interconnection line (VCT); and
a first division structure spaced apart from the gate electrode in the first direction and extending in the second direction (ASS),
wherein the first division structure penetrates the device isolation layer and the substrate (Fig 5),
the bottom surface of the substrate is at a first level, and the first division structure has a smallest width at the first level, when measured in the first direction (See Rejections from Claim 15 regarding tapering widths of the division structure).
Regarding Claim 17, See rejections from Claim 16, 10 and 1 above, as they would be considered repeated here.
Regarding Claim 19, See rejections from Claim 16, 10 and 1 above, as they would be considered repeated here.
Allowable Subject Matter
Claims 4, 5, 12, 18, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Specifically, Shih (US 11830765 B2), Su, (US 11830765 B2), Kim (US 20210327876 A1) show similar semiconductor devices to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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