DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.16/161,578, filed on10/16/2018.
Election/Restrictions
Claims 4-7, 11, 15, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/13/2026.
Claims 1-3, 8-10, 12-14, and 16 are still pending.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1-3, 8-10, 12-14, 16 is/are objected to because of the following informalities:
Claim 1 recites “the shield structure” in Line L13 but should read –the conductive, radio frequency shield structure--.
Claim 2 recites “the shield structure” in Line L1 but should read –the conductive, radio frequency shield structure--.
Claim 3 recites “the shield structure” in Line L1 but should read –the conductive, radio frequency shield structure--.
Claim 8 recites “the shield structure” in Line L1 but should read –the conductive, radio frequency shield structure--.
Claim 9 recites “the shield structure” in Line L1 but should read –the conductive, radio frequency shield structure--.
Claim 10 recites “the conductive pillars” in Line L2 but should read –the plurality of conductive pillars--.
Claim 12 recites “the shield structure” in Line L15 but should read –the conductive, radio frequency shield structure--.
Claim 13 recites “the shield structure” in Line L1 but should read –the conductive, radio frequency shield structure--.
Claim 13 recites “the second shield structure” in Line L5 but should read –the second conductive, radio frequency shield structure--.
Claim 14 recites “the second shield structure” in Lines L1-2 but should read –the second conductive, radio frequency shield structure--.
Claim 16 recites “the first conductive pillars” in Line L3 but should read –the plurality of first conductive pillars--.
Claim 16 recites “the second conductive pillars” in Lines L3-4 but should read –the plurality of second conductive pillars--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pagaila et al. (US20120104573A1-Pagaila73).
Regarding claim 1, Pagaila73 discloses a microelectronic assembly (270-Fig 7), comprising:
a package substrate having a first surface and an opposing second surface (Package substrate 308 having first/bottom surface and opposite second/top surface-Examiner's annotated Fig 7);
a first die having a first surface and an opposing second surface (First die 292 having a first/bottom surface and second opposite/top surface-Examiner's annotated Fig 7),
wherein the first die is in a first dielectric layer (First die 292 having a first/bottom surface and second opposite/top surface, being in first dielectric layer 300-Examiner's annotated Fig 7, [0056] L3-12),
wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate (First dielectric layer 300 between substrate 308 and second dielectric layer 290-Examiner's annotated Fig 7), and
wherein the first surface of the first die is coupled to the second surface of the package substrate (First/bottom surface of first die 292 coupled to second/top surface of substrate 308-Examiner's annotated Fig 7);
a second die having a first surface and an opposing second surface (Second die 282 having a first/bottom surface and second opposite/top surface, being in second dielectric layer 290-Examiner's annotated Fig 7),
wherein the second die is in the second dielectric layer (Second die 282 being in second dielectric layer 290-[0056] L3-12, Examiner's annotated Fig 7), and
wherein the second dielectric layer is between the first dielectric layer and a third dielectric layer (Second dielectric layer 290 between first dielectric layer 300 and third dielectric layer 280-Examiner's annotated Fig 7);
a third die having a first surface and an opposing second surface (Third die 272 having a first/top surface and second opposite/bottom surface,-Examiner's annotated Fig 7),
wherein the third die is in the third dielectric layer (Third die 272 being in third dielectric layer 280-[0056] L3-12, Examiner's annotated Fig 7),
wherein the first surface of the third die is coupled to the second surface of the package substrate by a conductive pillar (First/top surface of third die 272 coupled to second/top surface of substrate 308 by conductive pillar 298 of conductive pillars second pillar 278/ pillar 288/ first pillar 298-Examiner's annotated Fig 7); and
a conductive, radio frequency shield structure (Conductive, radio frequency shield structure 304 surrounding conductive pillars 278/288/298- [0002]L1-5, [0009] L1-14, [0057] L15-27, Fig 7),
wherein the shield structure surrounds the conductive pillar (Conductive, radio frequency shield structure 304 surrounding conductive pillars 278/288/298 so first conductive pillar 298-Examiner's annotated Fig 7).
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Regarding claim 2, Pagaila73 discloses all the elements of claim 1, as noted above.
Pagaila73 further discloses a microelectronic assembly
wherein the shield structure is coupled to a ground connection on the package substrate (Shield structure 304 coupled to a ground connection 310 on the package substrate 308-[0057] L15-27, Fig 7).
Regarding claim 3, Pagaila73 discloses all the elements of claim 1, as noted above.
Pagaila73 further discloses a microelectronic assembly
wherein the shield structure is coupled to a ground connection on the third die (Shield structure 304 coupled to a ground connection 276/274 on third die 272 through pillar structure 278/288/298 and ground connection 310 on the package substrate 308-[0057] L15-27, Examiner's annotated Fig 7).
Regarding claim 12, Pagaila73 discloses a computing device (computing device 10 -[0030] L1-6), comprising:
a microelectronic assembly (270-Fig 7), comprising:
a package substrate having a first surface and an opposing second surface (Package substrate 308 having first/bottom surface and opposite second/top surface-Examiner's annotated Fig 7);
a first die having a first surface and an opposing second surface (First die 292 having a first/bottom surface and second opposite/top surface-Examiner's annotated Fig 7),
wherein the first die is in a first dielectric layer (First die 292 having a first/bottom surface and second opposite/top surface, being in first dielectric layer 300-Examiner's annotated Fig 7, [0056] L3-12),
wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate (First dielectric layer 300 between substrate 308 and second dielectric layer 290-Examiner's annotated Fig 7), and
wherein the first surface of the first die is coupled to the second surface of the package substrate (First/bottom surface of first die 292 coupled to second/top surface of substrate 308-Examiner's annotated Fig 7);
a second die having a first surface and an opposing second surface (Second die 282 having a first/top surface and second opposite/bottom surface-Examiner's annotated Fig 7),
wherein the second die is in the second dielectric layer (Second die 282 being in second dielectric layer 290-[0056] L3-12, Examiner's annotated Fig 7), and
wherein the second dielectric layer is between the first dielectric layer and a third dielectric layer (Second dielectric layer 290 between first dielectric layer 300 and third dielectric layer 280-Examiner's annotated Fig 7);
a third die having a first surface and an opposing second surface (Third die 272 having a first/top surface and second opposite/bottom surface,-Examiner's annotated Fig 7),
wherein the third die is in the third dielectric layer (Third die 272 being in third dielectric layer 280-[0056] L3-12, Examiner's annotated Fig 7), and
wherein the first surface of the third die is coupled to the second surface of the package substrate by a first conductive pillar (First/top surface of third die 272 coupled to second/top surface of substrate 308 by first conductive pillar 298 of conductive pillars second pillar 278/ pillar 288/ first pillar 298, to ground connection 310-Examiner's annotated Fig 7), and
wherein the first surface of the third die is coupled to the second surface of the second die by a second conductive pillar (First/top surface of third die 272 coupled to second/top surface of second die 288 by second conductive pillar 278 of second pillar 278/ pillar 288/ first pillar 298-Examiner's annotated Fig 7); and
a conductive, radio frequency shield structure (Conductive, radio frequency shield structure 304 surrounding first conductive pillar 298 of 278/288/298- [0002]L1-5, [0009] L1-14, [0057] L15-27, Fig 7),
wherein the shield structure surrounds the conductive pillar (Conductive, radio frequency shield structure 304 surrounding conductive pillar 278/288/298 so first conductive pillar 298-Examiner's annotated Fig 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US20120104573A1-Pagaila73) in view of Han et al. (US 20190037683 A1-Han83).
Regarding claim 8, Pagaila73 discloses all the elements of claim 1, as noted above.
Pagaila73 does not disclose a microelectronic assembly
wherein the shield structure has a width between 20 microns and 200 micron.
Han83 teaches a microelectronic assembly
wherein the shield structure has a width between 20 microns and 200 microns (width of shield 103 between 80 to 100 microns so between 20 microns and 200 microns-[0041] L 9-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Pagaila73, as taught by Han83 for the purpose of reducing the height of the electronic apparatus (Han83:[0003]).
Regarding claim 9, Pagaila73 discloses all the elements of claim 1, as noted above.
Pagaila73 does not disclose a microelectronic assembly
wherein the shield structure has a height between 50 microns and 1000 microns.
Han83 teaches a microelectronic assembly
wherein the shield structure has a height between 50 microns and 1000 microns (height of shield 103 between 800 to 1000 microns so between 250 microns and 1000 microns-[0041] L 9-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Pagaila73, as taught by Han83 for the purpose of reducing the height of the electronic apparatus (Han83:[0003]).
Claim(s) 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US20120104573A1-Pagaila73) in view of Zhang et al. (WO 2017111830 A1-Zhang30).
Regarding claim 10, Pagaila73 discloses all the elements of claim 1, as noted above.
Pagaila73 does not disclose a microelectronic assembly
wherein the conductive pillar is one of a plurality of conductive pillars, and wherein a pitch of the conductive pillars is between 10 microns and 500 microns.
Zhang30 teaches a microelectronic assembly
wherein the conductive pillar is one of a plurality of conductive pillars, and wherein a pitch of the conductive pillars is between 10 microns and 500 microns (pitch width PW being between 60 and 200 microns so between 10 and 500 microns-page 21 L 16-34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Pagaila73, as taught by Zhang30 for the purpose of reducing the cross walk talk between signal (Zhang30: Abstract).
Regarding claim 16, Pagaila73 discloses all the elements of claim 12, as noted above.
Pagaila73 does not disclose a microelectronic assembly
wherein the first conductive pillar is one of a plurality of first conductive pillars,
wherein the second conductive pillar is one of a plurality of second conductive pillars, and
wherein a pitch of the first conductive pillars is different from a pitch of the second conductive pillars.
Zhang30 teaches a microelectronic assembly
wherein the first conductive pillar is one of a plurality of first conductive pillars (First/Top Left conductive pillar 130 of the plurality of first/Left column conductive pillars 130 as indicated in the dashed line rectangle, having a pitch PL-Examiner's annotated Fig 1A),
wherein the second conductive pillar is one of a plurality of second conductive pillars (Second/Second top Right conductive pillar 130 of the plurality of second conductive pillars 130 as indicated in the diagonal dashed line rectangle, having a pitch PD-Examiner's annotated Fig 1A), and
wherein a pitch of the first conductive pillars is different from a pitch of the second conductive pillars (Pitch PL being different than pitch PD-Examiner's annotated Fig 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Pagaila73, as taught by Zhang30 for the purpose of reducing the cross walk talk between signal (Zhang30: Abstract).
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Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US20120104573A1-Pagaila73) in view of Han et al. (US 20190037683 A1-Han83)
Regarding claim 13, Pagaila73 discloses all the elements of claim 12, as noted above.
Pagaila73 further discloses a computing device
wherein the shield structure is a first shield structure (first shield structure 304-Examiner's annotated Fig 7);
and the microelectronic assembly further comprises:
a third conductive pillar (Third conductive pillar 288-Examiner's annotated Fig 7),
wherein the first surface of the second die is coupled to the second surface of the package substrate by the third conductive pillar (First/top surface of second die 282 coupled to second/top surface of the substrate 308 by third conductive pillar 288 of conductive pillars first pillar 278/ third pillar 288/ second pillar 298-Examiner's annotated Fig 7);
Pagaila73 does not explicitly disclose a computing device wherein a microelectronic assembly further comprises:
a second conductive, radio frequency shield structure,
wherein the second shield structure surrounds the third conductive pillar.
Falcon72 teaches a computing device wherein a microelectronic assembly further comprises:
a second conductive, shield structure ( Left/second Copper so conductive shield structure 108-Fig 1, Fig 2A, [0032] L7-9),
wherein the second shield structure surrounds the third conductive pillar (Left/second Copper so conductive shield structure 108 surrounding third pillar 106-Fig 1, Fig 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Pagaila73, as taught by Falcon72 for the purpose of achieving desired isolation (Falcon72: [0053]).
Falcon72 does not explicitly teach a second conductive, radio frequency shield structure.
Pagaila73 teaches a computing device using metal enclosures to shield devices from RFI by having a faraday cage, and that the conductive material for the enclosure can be copper so any copper enclosure will shield devices from RFI ([0008] L1-7, [0045]L 1-16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the second Copper shield structure of Falcon72, as taught by Pagaila73 for the purpose of obtaining a second conductive, radio frequency shield structure (Pagaila73: [0045]).
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Regarding claim 14, Pagaila73 and Falcoon72 combination discloses all the elements of claim 13, as noted above.
Falcon72 further teaches a computing device
wherein the first shield structure and the second shield structure include copper ([0032] L7-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Pagaila73, as taught by Falcon72 for the purpose of achieving desired isolation (Falcon72: [0053]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/16/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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