DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on May 29, 2026, is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17, 21, 23, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0369328 (“DAVIES”).
Regarding claim 17, DAVIES teaches a method for forming an integrated chip (FIG. 6), the method comprising: etching a semiconductor waveguide layer to delimit a base portion (602, 603) of the semiconductor waveguide layer extending laterally over a substrate (606) and to delimit a ridge portion (604) of the semiconductor waveguide layer protruding upward from the base portion; depositing one or more dielectric layers (609) over the semiconductor waveguide layer; etching the one or more dielectric layers to form a first opening (left-hand side of the gap below element 607, corresponding to element 308 of Fig. 5) and a second opening (right-hand side of the gap below element 607, corresponding to element 308 of Fig. 5) in the one or more dielectric layers on opposite sides of the ridge portion of the semiconductor waveguide layer, the first opening and the second opening uncovering a first part and a second part of the base portion of the semiconductor waveguide layer, respectively (FIG. 6); etching the one or more dielectric layers to form a third opening (607) in the one or more dielectric layers, the third opening over the first and second openings and over the ridge portion of the semiconductor waveguide layer (FIG. 6); depositing a conductive material in the first and second openings to form a first heater contact (612) in the first opening and to form a second heater contact (611) in the second opening; and depositing a conductive material in the third opening to form a conductive heater line (610) in the third opening and on the first and second heater contacts.
Regarding claim 21, DAVIES teaches that the ridge portion, the first heater contact, the second heater contact, and the conductive heater line are elongated in a common direction (FIG. 6).
Regarding claim 23, DAVIES teaches a method for forming an integrated chip (FIG. 6), the method comprising: etching a semiconductor waveguide layer to form a ridge portion (604) of the semiconductor waveguide layer which protrudes upward from a base portion (602, 603) of the semiconductor waveguide layer; depositing a first dielectric layer (609) over the semiconductor waveguide layer; etching the first dielectric layer to uncover a first part of the base portion of the semiconductor waveguide layer and to uncover a second part of the base portion of the semiconductor waveguide layer, wherein the first part of the base portion is spaced from the ridge portion in a first direction, and wherein the second part of the base portion is spaced from the ridge portion in a second direction opposite the first direction (FIG. 6); forming a first heater contact (612) on the first part of the base portion and a second heater contact (611) on the second part of the base portion; and forming a conductive heater line (610) extending over the ridge portion from a top surface of the first heater contact to a top surface of the second heater contact.
Regarding claim 30, DAVIES teaches a method of forming an integrated chip (FIG. 6), the method comprising: forming a semiconductor waveguide layer over a substrate so that a base portion (602, 603) of the semiconductor waveguide layer extends laterally over the substrate and a ridge portion (604) of the semiconductor waveguide layer protrudes upward from the base portion; forming a first conductive heater contact (612) on the base portion of the semiconductor waveguide layer and laterally spaced from the ridge portion of the semiconductor waveguide layer in a first direction; forming a second conductive heater contact (611) on the base portion of the semiconductor waveguide layer and laterally spaced from the ridge portion of the semiconductor waveguide layer in a second direction opposite the first direction; and forming a conductive heater line (610) on and coupled to the first conductive heater contact, on and coupled to the second conductive heater contact, and vertically spaced over the ridge portion of the semiconductor waveguide layer (FIG. 6).
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over DAVIES.
DAVIES teaches the limitations of the base claim 23. The remaining limitations appear to involve mere duplication of parts. It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). As such, it would have been obvious to one of ordinary skill in the art at the effective filing date to duplicate the parts in the method of DAVIES as set forth in the instant claim.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over DAVIES in view of US 2015/0125111 (“ORCUTT”).
DAVIES teaches the limitations of the base claim 17. DAVIES does not teach forming a cavity directly under the ridge portion of the semiconductor waveguide layer, the cavity delimited by a bottom surface of the semiconductor waveguide layer and one or more surfaces of the substrate. ORCUTT teaches forming a cavity (270) directly under a ridge portion (portions of 280 corresponding to elements 272) of a semiconductor waveguide layer, the cavity delimited by a bottom surface of the semiconductor waveguide layer and one or more surfaces of the substrate (FIG. 2C; par. [0064]). It would have been obvious to one of ordinary skill in the art at the effective filing date to form the cavity of ORCUTT in the method of DAVIES. The motivation would have been to enhance a desired modal profile.
Claims 20, 27, 28, 33, 35, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over DAVIES in view of US 2021/0313771 (“KOSLOWSKI”).
Regarding claims 20 and 27, DAVIES teaches the limitations of the base claims 17 and 23. DAVIES does not teach forming a cavity between the ridge portion and the conductive heater line and between the ridge portion and the first and second heater contacts. KOSLOWSKI teaches forming a cavity between a ridge portion and a conductive heater line and between the ridge portion and first and second heater contacts (pars. [0037]-[0042]). It would have been obvious to one of ordinary skill in the art at the effective filing date to form the cavity of KOSLOWSKI in the method of DAVIES. The motivation would have been to better achieve heating uniformity.
Regarding claim 28, DAVIES in view of KOSLOWSKI renders obvious the limitations of the base claim 27. The remaining limitations appear to involve mere duplication of parts. It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). As such, it would have been obvious to one of ordinary skill in the art at the effective filing date to duplicate the parts in the method of DAVIES as set forth in the instant claim.
Regarding claim 33, DAVIES teaches the limitations of the base claim 30. DAVIES does not teach forming a cavity between a top surface of the ridge portion of the semiconductor waveguide layer and a bottom surface of the conductive heater line, between a first sidewall of the ridge portion of the semiconductor waveguide layer and a sidewall of the first conductive heater contact, and between a second sidewall of the ridge portion of the semiconductor waveguide layer and a sidewall of the second conductive heater contact. KOSLOWSKI teaches forming a cavity between a top surface of the ridge portion of the semiconductor waveguide layer and a bottom surface of the conductive heater line, between a first sidewall of the ridge portion of the semiconductor waveguide layer and a sidewall of the first conductive heater contact, and between a second sidewall of the ridge portion of the semiconductor waveguide layer and a sidewall of the second conductive heater contact (pars. [0037]-[0042]). It would have been obvious to one of ordinary skill in the art at the effective filing date to form the cavity of KOSLOWSKI in the method of DAVIES. The motivation would have been to better achieve heating uniformity.
Regarding claims 35 and 36, DAVIES teaches the limitations of the base claim 30. DAVIES does not teach forming a cavity under a bottom surface of the base portion of the semiconductor waveguide layer and extending under the first conductive heater contact, the ridge portion, and the second conductive heater contact, wherein the cavity is delimited by the bottom surface of the base portion and an upper surface of the substrate. KOSLOWSKI teaches forming a cavity under a bottom surface of a base portion of a semiconductor waveguide layer and extending under a first conductive heater contact, a ridge portion, and a second conductive heater contact, wherein the cavity is delimited by the bottom surface of the base portion and an upper surface of the substrate (pars. [0037]-[0042]). It would have been obvious to one of ordinary skill in the art at the effective filing date to form the cavity of KOSLOWSKI in the method of DAVIES. The motivation would have been to better achieve heating uniformity.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over DAVIES in view of US 2015/0037974 (“LU”).
DAVIES teaches the limitations of the base claim 17. DAVIES does not teach forming a barrier layer over the one or more dielectric layers, wherein the barrier layer extends along a sidewall of the first heater contact, a lower surface of the conductive heater line, and a sidewall of the second heater contact. LU teaches forming a barrier layer over one or more dielectric layers, wherein the barrier layer extends along a sidewall of a first heater contact, a lower surface of a conductive heater line, and a sidewall of the second heater contact (par. [0018]; FIG. 5). It would have been obvious to one of ordinary skill in the art at the effective filing date to form the barrier layer of LU in the method of DAVIES. The motivation would have been to better maintain dielectric integrity.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over DAVIES in view of US 2023/0096775 (“NEDOVIC”).
DAVIES teaches the limitations of the base claim 23. DAVIES does not teach that the ridge portion of the semiconductor waveguide layer extends in a closed ring, wherein the first heater contact and the second heater contact are on the base portion of the semiconductor waveguide layer outside of the closed ring, the method further comprising: forming a third heater contact on the base portion inside of the closed ring and between the first heater contact and the second heater contact, wherein the conductive heater line further extends to a top surface of the third heater contact.. NEDOVIC teaches that a ridge portion of a semiconductor waveguide layer extends in a closed ring, wherein a first heater contact and a second heater contact are on a base portion of the semiconductor waveguide layer outside of the closed ring, the method further comprising: forming a third heater contact on the base portion inside of the closed ring and between the first heater contact and the second heater contact, wherein the conductive heater line further extends to a top surface of the third heater contact (FIG. 2; par. [0005]). It would have been obvious to one of ordinary skill in the art at the effective filing date to extend the ridge portion of DAVIES in a closed ring, as taught by NEDOVIC. The motivation would have been to enhance resonant performance.
Allowable Subject Matter
Claims 18, 26, 29, 31, 32, and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 18, the prior art of record, whether taken individually or in combination, when considered in light of the claimed subject matter as a whole as interpreted in light of the Specification as originally filed, fails to disclose or render obvious doping the semiconductor waveguide layer to form a first doped region having a first doping type in the base portion of the semiconductor waveguide layer, to form a second doped region having the first doping type in the base portion of the semiconductor waveguide layer, and to form a third doped region in the ridge portion of the semiconductor waveguide layer and directly between the first doped region and the second doped region, wherein a doping concentration of the first doped region and a doping concentration of the second doped region are greater than a doping concentration of the third doped region, wherein the first opening and the second opening are formed directly over the first doped region and the second doped region, respectively.
Regarding claim 26, the prior art of record, whether taken individually or in combination, when considered in light of the claimed subject matter as a whole as interpreted in light of the Specification as originally filed, fails to disclose or render obvious forming a first doped region having a first doping type in the first part of the base portion of the semiconductor waveguide layer; and forming a second doped region having the first doping type in the second part of the base portion of the semiconductor waveguide layer; and forming a third doped region having the first doping type in the ridge portion of the semiconductor waveguide layer and directly between the first doped region and the second doped region, wherein a doping concentration of the first doped region and a doping concentration of the second doped region are greater than a doping concentration of the third doped region.
Regarding claim 29, the prior art of record, whether taken individually or in combination, when considered in light of the claimed subject matter as a whole as interpreted in light of the Specification as originally filed, fails to disclose or render obvious that an upper surface of the base portion, an upper surface of the ridge portion, a lower surface of the conductive heater line, a sidewall of the first heater contact, and a sidewall of the second heater contact delimit the first cavity, and wherein a lower surface of the base portion delimits the second cavity.
Regarding claims 31 and 32, the prior art of record, whether taken individually or in combination, when considered in light of the claimed subject matter as a whole as interpreted in light of the Specification as originally filed, fails to disclose or render obvious forming a first doped region having a first doping type in the base portion of the semiconductor waveguide layer; and forming a second doped region having the first doping type in the base portion of the semiconductor waveguide layer, wherein the first conductive heater contact is in contact with the first doped region, and wherein the second conductive heater contact is in contact with the second doped region.
Regarding claim 34, the prior art of record, whether taken individually or in combination, when considered in light of the claimed subject matter as a whole as interpreted in light of the Specification as originally filed, fails to disclose or render obvious that the cavity is delimited by the top surface of the ridge portion, the bottom surface of the conductive heater line, the first sidewall of the ridge portion, the sidewall of the first conductive heater contact, the second sidewall of the ridge portion, the sidewall of the second conductive heater contact, and an upper surface of the base portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY M BLEVINS whose telephone number is (571)272-8581. The examiner can normally be reached Monday - Friday.
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/JERRY M BLEVINS/Primary Examiner, Art Unit 2874
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