Prosecution Insights
Last updated: July 17, 2026
Application No. 18/630,326

SEMICONDUCTOR MODULE

Non-Final OA §112
Filed
Apr 09, 2024
Priority
Jun 15, 2023 — JP 2023-098595
Examiner
DUREN, TIMOTHY EDWARD
Art Unit
Tech Center
Assignee
MIRISE Technologies Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
37 granted / 47 resolved
+18.7% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
20 currently pending
Career history
84
Total Applications
across all art units

Statute-Specific Performance

§103
82.6%
+42.6% vs TC avg
§102
7.6%
-32.4% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 47 resolved cases

Office Action

§112
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . General Remarks 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection. 3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. 4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Drawings 5. The drawings are objected to because Figure 1 does not contain coordinate axes to describe the directions pertaining to claim 1. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “Semiconductor Power Module for Three-Level Inverter Devices” Appropriate correction is required. Claim Objections 7. Claim 1 is objected to because of the following informalities: Claim 1, line 20 recites “a fourth terminal that extended…,” wherein the grammar is improper. Applicant is advised to amend claim 1, line 20 to recite “a fourth terminal that extends…” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 8. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites in the preamble “A semiconductor module comprising:” and continues to recite “the first module includes: a first terminal… [and] the second module includes: a fourth terminal…” The semiconductor module is not distinguishable from the first and second modules, therefore said modules have an unclear description. Applicant is advised to further distinguish between the semiconductor module and first and second modules of claim 1, e.g. the first and second modules may be amended to “first and second diode modules” or “first and second transistor modules.” For examination on the merits, claim 1 will be interpreted in its broadest reasonable interpretation as comprising of semiconductor power module comprising of a first and second transistor module. The dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Allowable Subject Matter 9. Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Regarding claim 1, the closest prior art Nishiyama, Tomohiro Tokyo (Pub No. US 20180342440 A1) (hereinafter, Nishiyama) in view of Hayashiguchi, Masashi Kyoto-shi (Pub No. US 20240204685 A1) (hereinafter, Hayashiguchi) either singularly or in combination fails to anticipate or render obvious “A semiconductor module comprising: a first module; and a second module, wherein the first module includes: a first terminal extending in a first direction; a first element that includes a first electrode connected to the first terminal, a second electrode, a first gate electrode that causes a current to flow between the first electrode and the second electrode in response to a voltage application, and a first diode connected to the first electrode and the second electrode; a second element that includes a third electrode connected to the second electrode, a fourth electrode, a second gate electrode that causes a current to flow between the third electrode and the fourth electrode in response to a voltage application, and a second diode connected to the third electrode and the fourth electrode; a second terminal that is connected to the third electrode, extended in the first direction, and is to be connected to a load; a third terminal that is connected to the fourth electrode and extended in the first direction, the second module includes: a fourth terminal that extended in the first direction and connected to the second terminal so as to connect the first module and the second module to each other; a third element that includes a fifth electrode connected to the fourth terminal, a sixth terminal, a third gate electrode that causes a current to flow between the fifth electrode and the sixth electrode in response to a voltage application, and a third diode connected to the fifth electrode and the sixth electrode; a fourth element that includes a seventh electrode, an eighth electrode connected to the sixth electrode, a fourth gate that causes a current to flow between the seventh electrode and the eighth electrode in response to a voltage application, and a fourth diode connected to the seventh electrode and the eighth electrode; a fifth terminal that is connected to the seventh electrode and extended in the first direction; and a sixth terminal that is connected to the seventh electrode and extended in the first direction, the first module faces the second module in a thickness direction of the first module, and a direction of a current path in the first module is opposite to a direction of a current path in the second module,” in combination with all other limitations in the claim(s) as claimed and defined by applicant. In the instant case, re claim 1, Nishiyama discloses in Figure 25 a first and second module (LG1A/LG1B) comprising of the elements included in each module of claim 1. However, the direction of a current path of the first module is not disclosed to be opposite to a direction of a current path in the second module. Further, Hayashiguchi discloses in Figure 6 and paragraph [0162] a semiconductor module comprising of an upper arm path (path between terminals 41 and 44) and lower arm path (path between terminals 42 and 44) which create magnetic fields which cancel each other out, reducing parasitic inductance of the semiconductor module. However, Hayashiguchi’s semiconductor module does not comprise of an upper arm path and lower arm path (which may be interpreted as a first and second module in their broadest reasonable interpretation) with currents flowing in opposite directions. Additionally, the upper arm path and lower arm path do not comprise of the elements required by the first and second modules of claim 1. Finally, the invention of Nishiyama comprises of a first and second module which does not contain any of the elements of the first and second modules of Hayashiguchi, therefore no combination of the prior art elements may be combined to yield predictable results. (See MPEP § 2143 (I)) Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. [1] Sano, Tomohisa et al. (Pub No. US 20210143747 A1) discloses a power module applied to an electric power conversion device comprising upper-lower arm circuits connected to an electric power line in parallel such that surge voltage may be reduced. [2] Tsuyuno, Nobutake et al. (Pub No. US 20130119525 A1) discloses a power semiconductor unit applied to hybrid automobiles which comprises of a cooling structure which may prevent voids developing in of steps between heat radiation surfaces and heat sink electrodes. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /T.E.D./ Examiner Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Apr 09, 2024
Application Filed
Jun 12, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
91%
With Interview (+12.6%)
3y 4m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 47 resolved cases by this examiner. Grant probability derived from career allowance rate.

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