DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 7, 13, 16, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite “is delayed than a previous delay” in line 1 of claims 4, 7, 13, 16 and line 4 of claim 20. The comparison appears to be missing an operation/definition. For purposes of examination, the limitation will be construed as -- is delayed [more/less] than a previous delay --.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manohararajah et al. (US 2012/0110400 “Manohararajah”) in view of Jeter et al. (US 2016/0209866 “Jeter”).
Regarding claim 1, Manohararajah discloses a storage device comprising:
a memory device (memory system; para 0018); and
a controller (100; fig. 1) electrically coupled with the memory device,
wherein the controller (100) is configured to input first data bits (d0-d3; fig. 7A) to the memory device along with a first data strobe signal (DQS, i.e. “strobe”; fig. 7A para 0047),
the controller is configured to sweep a delay (sweep by applying a plurality of delays 701-706; fig. 7A) of the first data strobe signal (DQS, i.e. “strobe”) to determine pass or fail of the first data bits (i.e. determine successful read/writes for the first data bits d0-d3; para 0047), and
the controller is configured to adjust delays (adjusted strobe delay; fig. 7B) of the first data bits (d0-d3; fig. 7B) to align the first data bits with the first data strobe signal (i.e. aligning by centering the first data bits d0-d3 with respect to the strobe; fig. 7B) based on a determination of the pass or the fail (i.e. based on the successful read/writes).
Manohararajah does not expressly disclose a nonvolatile memory device including a plurality of memory blocks.
Jeter discloses a nonvolatile memory (memory 158 including nonvolatile memory; fig. 1 para 0014) device including a plurality of memory blocks (storage locations 29; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 2, Jeter discloses the storage device of claim 1, wherein the controller is configured to input the first data bits (DQ(Write); fig. 1) along with the first data strobe signal (WrDQS; fig. 1) having a first delay (an applied delay to WrDQS; para 0016), and read second data bits (DQ(Read); fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 3, Jeter discloses the storage device of claim 2, wherein the first delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 4, Jeter discloses the storage device of claim 2, wherein the first delay is delayed than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 5, Jeter discloses the storage device of claim 2, wherein the controller is configured to input the first data bits along with the first data strobe signal having a second delay (any point in a calibration procedure after the first delay represents a second delay; fig. 2), and read second data bits (DQ(Read); fig. 1) along with the second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 6, Jeter discloses the storage device of claim 5, wherein the second delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 7, Jeter discloses the storage device of claim 5, wherein the second delay is delayed than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 9, Manohararajah discloses the storage device of claim 1, wherein the controller is configured to sweep the delay of the first data strobe signal at least twice (fig. 7A).
Regarding claim 10, Manohararajah discloses a method of operating a storage device including a memory device and a controller, the method comprising:
inputting, by the controller (100; fig. 1), first data bits (d0-d3; fig. 7A) to the memory device (memory system; para 0018) along with a first data strobe signal (DQS, i.e. “strobe”; fig. 7A para 0047) while sweeping a delay of the first data strobe signal (sweep by applying a plurality of delays 701-706; fig. 7A) to determine pass or fail of the first data bits (i.e. determine successful read/writes for the first data bits d0-d3; para 0047); and
adjusting, by the controller, delays (adjusted strobe delay; fig. 7B) of the first data bits (d0-d3; fig. 7B) to align the first data bits with the first data strobe signal (i.e. aligning by centering the first data bits d0-d3 with respect to the strobe; fig. 7B) based on a determination of the pass or the fail (i.e. based on the successful read/writes).
Manohararajah does not expressly disclose a nonvolatile memory device.
Jeter discloses a nonvolatile memory device (memory 158 including nonvolatile memory; fig. 1 para 0014).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 11, Jeter discloses the method of claim 10, wherein the inputting comprises: inputting the first data bits (DQ(Write); fig. 1) along with the first data strobe signal (WrDQS; fig. 1) having a first delay (an applied delay to WrDQS; para 0016), and reading second data bits (RdDQS; fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 12, Jeter discloses the method of claim 11, wherein the first delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 13, Jeter discloses the method of claim 11, wherein the first delay is delayed than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 14, Jeter discloses the method of claim 10, wherein the inputting further comprises: inputting the first data bits along with the first data strobe signal having a second delay (any point in a calibration procedure after the first delay represents a second delay; fig. 2); and reading second data bits (DQ(Read); fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 15, Jeter discloses the method of claim 14, wherein the second delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 16, Jeter discloses the method of claim 14, wherein the second delay is delayed than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 18, Manohararajah discloses the method of claim 10, wherein the inputting comprises: sweeping the delay of first data strobe signal at least twice (fig. 7A).
Regarding claim 19, Manohararajah discloses a storage device comprising:
a memory device (memory system; para 0018); and
a controller (100; fig. 1) electrically coupled with the nonvolatile memory device,
wherein the controller (100) is configured to sweep a delay of the first data strobe signal to a first delay (sweep by applying a plurality of delays 701-706, essentially including a first delay; fig. 7A), input first data bits (d0-d3; fig. 7A) along with the first data strobe signal (DQS, i.e. “strobe”; fig. 7A para 0047) having the first delay (i.e. as applied; fig. 7A), and determine pass or fail of the first data bits (i.e. determine successful read/writes for the first data bits d0-d3; para 0047),
the controller (100) is configured to sweep the delay of the first data strobe signal to a second delay (i.e. a second delay different from the first delay; fig. 7A), input the first data bits along with the first data strobe signal having the second delay (first data bits are input with the strobe having the second delay; fig. 7A), and determine the pass or the fail of the first data bits (i.e. determine successful read/writes for the first data bits d0-d3; para 0047), and
the controller (100) is configured to adjust delays (adjusted strobe delay; fig. 7B) of the first data bits (d0-d3; fig. 7B) to align the first data bits with the first data strobe signal (i.e. aligning by centering the first data bits d0-d3 with respect to the strobe; fig. 7B) based on a determination of the pass or the fail (i.e. based on the successful read/writes).
Manohararajah does not expressly disclose a nonvolatile memory device including a plurality of memory blocks, read second data bits along with a second data strobe signal from the nonvolatile memory device, read the second data bits along with the second data strobe signal from the nonvolatile memory device.
Jeter discloses a nonvolatile memory (memory 158 including nonvolatile memory; fig. 1 para 0014) device including a plurality of memory blocks (storage locations 29; fig. 1), read second data bits (RdDQS; fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device, read the second data bits (RdDQS is read at each point of a calibration procedure; fig. 2) along with the second data strobe signal (RdDQS) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 20, Jeter discloses the storage device of claim 19, wherein one of the first delay and the second delay is more advanced than a previous delay of the first data strobe signal used in a previous write operation (any point in the calibration procedure after a first delay is a second delay, further, each point in the calibration is a write and read operation, the first delay and/or the second delay can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2), and
another one of the first delay and the second delay is delayed than the previous delay of the first data strobe signal used in the previous write operation (any point in the calibration procedure after a first delay is a second delay, further, the first delay and/or the second delay can be any point in the calibration that is more more/less delayed toward the lower/upper end than the previous delay of the previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manohararajah et al. (US 2012/0110400 “Manohararajah”) in view of Jeter et al. (US 2016/0209866 “Jeter”), further in view of Stott et al. (US 2018/0082725 “Stott”).
Regarding claim 8, Manohararajah does not expressly disclose the storage device of claim 2, wherein the nonvolatile memory device is configured to receive a read enable signal from the controller and output the second data strobe signal to the controller, and the second data strobe signal is delayed from the read enable signal.
Jeter discloses wherein the nonvolatile memory device is configured to receive a read enable signal (para 0015) from the controller and output the second data strobe signal (fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Stott discloses output the second data strobe signal to the controller (fig. 1B), and the second data strobe signal (152-2; fig. 1B) is delayed from the read enable signal (dynamically adjusting a timing offset between the enable signal and the data strobe signal; para 0034).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is further modifiable as taught by Stott for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0036 of Stott), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 17, Manohararajah does not expressly disclose the method of claim 11, further comprising: receiving, by the nonvolatile memory device, a read enable signal from the controller; and generating the second data strobe signal by delaying the read enable signal.
Jeter discloses receiving, by the nonvolatile memory device, a read enable signal from the controller (para 0015); and generating the second data strobe signal (fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Stott discloses by delaying the read enable signal (dynamically adjusting a timing offset between the enable signal and the data strobe signal; para 0034).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Manohararajah is further modifiable as taught by Stott for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0036 of Stott), which is common and well known in the prior art to secure the integrity of data storage.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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