DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed on 04/09/2024.
Claims 1-20 are pending.
Specification
The disclosure is objected to because of the following informalities:
[0085] “…the NIC 224 may be in direct communication…” should read “…the peripheral device 224 may be in direct communication…”.
Appropriate correction is required.
Claim Objections
Claims 10, 13-14, and 17-19 are objected to because of the following
informalities:
In Claim 10, “in memory of the peripheral device” should read “in memory of a peripheral device”.
In Claim 13, “wherein detecting a change in the value of the first index” should read “wherein detecting the change in the value of the first index”.
In Claim 17, “wherein ringing the DB” should read “wherein ringing a DB”.
Any claim not specifically mentioned above, is objected due to its dependency on an objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by ARRAMREDDY et al. Pub. No. US 2014/0280716 Al (hereafter ARRAMREDDY).
Regarding claim 1, ARRAMREDDY anticipates the invention as claimed, including: A system comprising one or more circuits to: monitor a value of a first index ([0033] “…Host CPU 400 can increment its producer index 402 to keep track of the number of transmission requests made to the networking device 420…”, Note: The producer index of the host is interpreted as the value of the first index); detect a change in the value of the first index ([0033] “…Host CPU 400 can increment its producer index 402 to keep track of the number of transmission requests made to the networking device 420…”, Note: The producer index of the host is incremented/changed); generate a control (ctrl) segment using at least one of the value of the first index and a queue number ([0024] “…Host software 201 can ring the doorbell, shown by arrow 233, by writing a value into a doorbell register 221. The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201. The doorbell register can comprise an SQ number and the number of transmission requests…”, Note: The SQ number and the number of transmission requests written into the doorbell register is interpreted as the ctrl segment); and write the ctrl segment to a control address ([0024] “…Host software 201 can also post the data packet in a data buffer 213 in host memory 210, shown by arrow 232. Host software 201 can ring the doorbell, shown by arrow 233, by writing a value into a doorbell register 221. The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201. The doorbell register can comprise an SQ number and the number of transmission requests…”, Note: The SQ number and the number of transmission requests written into the doorbell register is interpreted as the ctrl segment, and the allocated address space located in the networking device is interpreted as the control address).
Regarding claim 2, ARRAMREDDY anticipates: The system of claim 1, wherein the one or more circuits further: receive a prompt from an application ([0019] “This relates to methods and techniques to manage transmitting data packets for both high-throughput and low-latency operation, for applications such as high performance computing and message-based applications…”, Note: The data packets to be transmitted are interpreted as prompts); in response to the prompt, generate a work queue entry (WQE) ([0024] “…The host software can maintain one or more queues with entries corresponding to the data packets to be transmitted…”, Note: The entries in a queue corresponding to the data packets to be transmitted are interpreted as WQEs); and after generating the WQE, atomically increment a first counter ([0033] “…Host CPU 400 can increment its producer index 402 to keep track of the number of transmission requests made to the networking device 420…”, Note: The number of transmission requests made is interpreted as the first counter), wherein writing the ctrl segment to the control address causes the WQE to be read by a peripheral device ([0024] “…Host software 201 can also post the data packet in a data buffer 213 in host memory 210, shown by arrow 232. Host software 201 can ring the doorbell, shown by arrow 233, by writing a value into a doorbell register 221. The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201. The doorbell register can comprise an SQ number and the number of transmission requests … From the information in the doorbell register 221, the networking device 220 can determine which SQ to access by a read operation. The networking device 220 can perform a read of the SQ 211, shown by arrow 234, by a queue reader 223 to retrieve the WRB entry 212. Using the information in WRB entry 212, the networking device can use the pointer information, shown by arrow 235, given in the one or more SGEs of the WRB entry 212 to retrieve the data packet from a data buffer 213 located in host memory 210, shown by arrow 236. Retrieving the data packet can be performed by a data reader 224 located in the networking device 220.”, Note: The SQ number and the number of transmission requests written into the doorbell register is interpreted as the ctrl segment, the allocated address space located in the networking device is interpreted as the control address, the entries in a queue (SQ or send queue in prior art) corresponding to the data packets to be transmitted are interpreted as WQEs, and the networking device is interpreted as the peripheral device).
Regarding claim 3, ARRAMREDDY anticipates: The system of claim 2, wherein: one warp of a cooperative thread array (CTA) … and another warp of the CTA ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claims 1 and 2 are read on by the prior art). The other limitations are substantially the same as those of claims 1 and 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 4, ARRAMREDDY anticipates: The system of claim 2, wherein: one cooperative thread array (CTA) … another CTA ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claims 1 and 2 are read on by the prior art). The other limitations are substantially the same as those of claims 1 and 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 5, ARRAMREDDY anticipates: The system of claim 2, wherein the one or more circuits include: a central processing unit (CPU) to … a graphics processing unit (GPU) to ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claims 1 and 2 are read on by the prior art). The other limitations are substantially the same as those of claims 1 and 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 6, ARRAMREDDY anticipates: The system of claim 2, wherein the one or more circuits include: a data-path accelerator (DPA) to … a graphics processing unit (GPU) to ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claims 1 and 2 are read on by the prior art). The other limitations are substantially the same as those of claims 1 and 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 7, ARRAMREDDY anticipates: The system of claim 2, wherein a single thread ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claims 1 and 2 are read on by the prior art). The other limitations are substantially the same as those of claims 1 and 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 8, ARRAMREDDY anticipates: The system of claim 2, wherein monitoring the value, detecting the change, generating the ctrl segment, and writing the ctrl segment to the control address are performed in parallel with receiving the prompt, generating the WQE, and incrementing the first counter ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: As the limitations in claims 1 and 2 are not dependent on each other, the host of the prior art performs any logic with those limitations in parallel).
Regarding claim 9, ARRAMREDDY anticipates: The system of claim 2, wherein the peripheral device comprises at least one of a network interface controller (NIC), a graphical processing unit (GPU), and a solid-state drive (SSD) ([0040] “…Device 880 may include a network interface controller (NIC) (similarly termed as network interface card or network adapter), such as an Ethernet card, a host bus adapter (as for Fibre Channel), a converged network adapter (CNA) (as for supporting both Ethernet and Fibre Channel), or any other device having networking device functionality…”, [0042] “…The functions of the networking device in the examples of this disclosure may be implemented by device logic 882, which can represent any set of processors or circuitry performing the functions. Device 880 may be caused to perform the functions of the networking device in the examples of this disclosure when device logic 882 executes instructions stored in one or more machine-readable storage media, such as device memory 884…”, Note: The networking device is interpreted as the peripheral device).
Regarding claim 10, ARRAMREDDY anticipates: The system of claim 1, wherein the control address is in memory of the peripheral device ([0024] “…The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201…”, Note: The allocated address space located in the networking device is interpreted as the control address, and the networking device is interpreted as the peripheral device).
Regarding claim 11, ARRAMREDDY anticipates: The system of claim 1, wherein the control address is in memory of the system ([0024] “…The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201…”, Note: The allocated address space located in the networking device is interpreted as the control address, and the networking device is a part of the overall system).
Regarding claim 12, ARRAMREDDY anticipates: The system of claim 1, wherein the ctrl segment includes data associated with a plurality of queues ([0024] “…The host software can maintain one or more queues with entries corresponding to the data packets to be transmitted … The doorbell register can comprise an SQ number and the number of transmission requests…”, Note: The SQ (SQ or send queue) number and the number of transmission requests written into the doorbell register is interpreted as the ctrl segment).
Regarding claim 13, ARRAMREDDY anticipates: The system of claim 1, wherein detecting a change in the value of the first index comprises determining the value of the first index is greater than a value of a second index ([0033] “Referring back to FIG. 4, host software 401 can ring the doorbell 423, shown by arrow 435, by writing to the doorbell register 423 located on the networking device 420. The doorbell register 423 can be a mechanism to inform the networking device 420 of transmission requests and can include the SQ number. Host CPU 400 can increment its producer index 402 to keep track of the number of transmission requests made to the networking device 420. When the doorbell register 423 has been written to, the networking device 420 can also update its own producer index 424 to keep track of how many transmission requests were pushed by host software 401…”, Note: The producer index of the host is interpreted as the value of the first index, the producer index of the networking device is interpreted as the value of the second index, and the doorbell register contains the incremented producer index of the host which is greater than the producer index of the networking device).
Regarding claim 14, ARRAMREDDY anticipates: The system of claim 13, wherein the one or more circuits are further to set the value of the second index equal to the value of the first index after writing the ctrl segment to the control address ([0033] “Referring back to FIG. 4, host software 401 can ring the doorbell 423, shown by arrow 435, by writing to the doorbell register 423 located on the networking device 420. The doorbell register 423 can be a mechanism to inform the networking device 420 of transmission requests and can include the SQ number. Host CPU 400 can increment its producer index 402 to keep track of the number of transmission requests made to the networking device 420. When the doorbell register 423 has been written to, the networking device 420 can also update its own producer index 424 to keep track of how many transmission requests were pushed by host software 401…”, [0024] “…Host software 201 can also post the data packet in a data buffer 213 in host memory 210, shown by arrow 232. Host software 201 can ring the doorbell, shown by arrow 233, by writing a value into a doorbell register 221. The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201. The doorbell register can comprise an SQ number and the number of transmission requests…”, Note: The producer index of the host is interpreted as the value of the first index, the producer index of the networking device is interpreted as the value of the second index, the SQ number and the number of transmission requests (incremented producer index of the host) written into the doorbell register is interpreted as the ctrl segment, and the allocated address space located in the networking device is interpreted as the control address).
Regarding claim 15, ARRAMREDDY anticipates: The system of claim 1, wherein the one or more circuits are further to update a doorbell record (DBR) with the value of the first index in response to the change in the value of the first index ([0033] “Referring back to FIG. 4, host software 401 can ring the doorbell 423, shown by arrow 435, by writing to the doorbell register 423 located on the networking device 420. The doorbell register 423 can be a mechanism to inform the networking device 420 of transmission requests and can include the SQ number. Host CPU 400 can increment its producer index 402 to keep track of the number of transmission requests made to the networking device 420…”, [0024] “…Host software 201 can also post the data packet in a data buffer 213 in host memory 210, shown by arrow 232. Host software 201 can ring the doorbell, shown by arrow 233, by writing a value into a doorbell register 221. The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201. The doorbell register can comprise an SQ number and the number of transmission requests…”, Note: The doorbell register is interpreted as the DBR, and the number of transmission requests (incremented producer index of the host) is the value of the first index).
Regarding claim 16, ARRAMREDDY anticipates: The system of claim 1, wherein the control address is in a cache of a graphics processing unit (GPU) ([0024] “…The doorbell register 221 can be an allocated address space located in the networking device 220 that can be used as a mechanism to notify the networking device 220 when a transmit operation has been requested by host software 201…”, [0040] “…Device 880 may include a network interface controller (NIC) (similarly termed as network interface card or network adapter), such as an Ethernet card, a host bus adapter (as for Fibre Channel), a converged network adapter (CNA) (as for supporting both Ethernet and Fibre Channel), or any other device having networking device functionality…”, [0042] “…The functions of the networking device in the examples of this disclosure may be implemented by device logic 882, which can represent any set of processors or circuitry performing the functions. Device 880 may be caused to perform the functions of the networking device in the examples of this disclosure when device logic 882 executes instructions stored in one or more machine-readable storage media, such as device memory 884…”, Note: The allocated address space located in the networking device is interpreted as the control address, and any networking device (i.e. GPU) with any memory is read on by the prior art).
Regarding claim 17, ARRAMREDDY further anticipates: A device, comprising one or more circuits to execute: a first thread to … a second thread to ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claims 1 and 2 are read on by the prior art). The other limitations are substantially the same as those of claims 1 and 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 18, ARRAMREDDY further anticipates: The device of claim 17, wherein: one warp of a cooperative thread array (CTA) executes the first thread ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claim 17 are read on by the prior art); and another warp of the CTA executes the second thread ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claim 17 are read on by the prior art).
Regarding claim 19, ARRAMREDDY further anticipates: The device of claim 17, wherein: one cooperative thread array (CTA) executes the first thread ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claim 17 are read on by the prior art); and another CTA executes the second thread ([0040] “…Host 870 may include a computer, a server, a mobile device, or any other devices having host functionality…”, [0041] “…The functions of the host in the examples of this disclosure may be implemented by host logic 872, which can represent any set of processors or circuitry performing the functions. Host 870 may be caused to perform the functions of the host in the examples of this disclosure when host logic 872 executes instructions stored in one or more machine-readable storage media, such as host memory 874…”, Note: Any type of processing device or logic which performs the limitations of claim 17 are read on by the prior art).
Regarding claim 20, it is a process claim whose limitations are substantially the same as those of claim 1. Accordingly, it is rejected for substantially the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In particular, US 20030065856 A1 is cited because it discloses doorbell ringing to notify an HCA that a WQE is ready to be executed.
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/J.C.T./Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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