DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges the amendments to claims 1, 8, 11, and 18 in the reply dated 12 August 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2, 14, and 19 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The phrases “...a distance from lateral surfaces of the plurality of first pads to the recesses is in a range of about 2 micrometers to about 5 micrometers” (Claim 19) and “...a distance from a lateral surface of the second pad to the second recess is in a range of about 2 micrometers to about 5 micrometers” (Claims 2 and 14) are not clarified by the presentation of the claimed invention, wherein the lateral surface of a pad is undefined. The specification states a distance of about 2 micrometers to about 5 micrometers without further specification of the measurement location in drawings or written definition.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 7, 10-13, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokoyama (JP 2011176011 A, hereinafter “Yokoyama”).
Regarding Claim 1 - Yokoyama discloses a semiconductor package comprising: a first substrate (101 [0059] and Fig. 3) that comprises a central area (central, annotated Fig. 3) and a peripheral area surrounding the central area (peripheral, annotated Fig. 3); a protection layer on the first substrate (105 [0075] and Fig. 2); a first pad on the protection layer in the central area, the first pad penetrating the protection layer and being directly attached to the first substrate (combination of 102 and 106 [0062] and Fig. 2, in central of annotated Fig. 3); a second pad on the first substrate in the peripheral area (combination of 102 and 106 [0062] and Fig. 2, in peripheral of annotated Fig. 3); a first solder on and coupled to the first pad (107 [0062] and Fig. 2 in central, annotated Fig. 3); and a second solder on and coupled to the second pad (107 [0062] and Fig. 2 in peripheral, annotated Fig. 3), wherein the first pad has a first recess from a top surface of the first pad (103hs [0062] and Fig. 2), wherein the second pad has a second recess from a top surface of the second pad (103hr [0062] and Fig. 2), wherein a width of the second recess is greater than a width of the first recess in a first direction (103r > 103s Figs. 2 and 3), wherein a volume of the second solder is greater than a volume of the first solder (107r larger than 107s [0115] and Fig. 13), wherein the protection layer comprises holes that are respectively filled with the first pad and the second pad (Holes in 105 filled with 106 in Fig. 2), and wherein a width of the first pad is the same as a width of the second pad (All have width 102t, as in Fig. 6).
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Regarding Claim 3 - Yokoyama further discloses the semiconductor package of claim 1, wherein each of the first recess and the second recess has a circular planar shape, a tetragonal planar shape, a polygonal planar shape, or a cross planar shape (circular in Fig. 3).
Regarding Claim 4 - Yokoyama further discloses the semiconductor package of claim 1, wherein a height of the first pad and a height of the second pad are the same (Same diagram used for both, Fig. 2).
Regarding Claim 5 - Yokoyama further discloses the semiconductor package of claim 1, wherein a height of the first solder is about 90% to about 100% of a height of the second solder (Shown as 100% using Fig. 2 for both).
Regarding Claim 7 - Yokoyama further discloses the semiconductor package of claim 1, wherein a volume of an inner section of the second recess is greater than a volume of an inner section of the first recess (Second recess wider gives more volume than first recess, Figs. 2 and 3).
Regarding Claim 10 - Yokoyama further discloses the semiconductor package of claim 1, further comprising: a second substrate on the first substrate (110 [0062] and Fig. 2); and a fourth pad and a fifth pad on the second substrate (109 in central and 109 in peripheral, respectively), wherein the first solder connects the first pad to the fourth pad (109 connected by 107 to 106 and 102 in central, Fig. 2 and annotated Fig. 3), wherein the second solder connects the second pad to the fifth pad (109 connected by 107 to 106 and 102 in central, Fig. 2 and annotated Fig. 3), wherein a distance between the first substrate and the second substrate in the central area is about 90% to about 100% of a distance between the first substrate and the second substrate in the peripheral area (Shown as 100% using Fig. 2 for both).
Regarding Claim 11 - Yokoyama discloses a semiconductor package comprising: a semiconductor chip (101 [0059] and Fig. 3) that has a first region (central, annotated Fig. 3) and a second region spaced apart from the first region (peripheral, annotated Fig. 3); a protection layer on the semiconductor chip (105 [0075] and Fig. 2); a first pad on the protection layer in the first region, the first pad penetrating the protection layer and being directly attached to the semiconductor chip (combination of 102 and 106 [0062] and Fig. 2, in central of annotated Fig. 3); a second pad on the protection layer in the second region, the second pad penetrating the protection layer and being directly attached to the semiconductor chip (combination of 102 and 106 [0062] and Fig. 2, in peripheral of annotated Fig. 3); a first solder on and coupled to the first pad (107 [0062] and Fig. 2 in central, annotated Fig. 3); and a second solder on and coupled to the second pad (107 [0062] and Fig. 2 in peripheral, annotated Fig. 3), wherein the first pad has a first recess from a top surface of the first pad (103hs [0062] and Fig. 2), wherein the second pad has a second recess from a top surface of the second pad (103hr [0062] and Fig. 2), wherein a volume of an inner section of the second recess is greater than a volume of an inner section of the first recess (Second recess wider gives more volume than first recess, Figs. 2 and 3), wherein a height of the first solder is about 90% to about 100% of a height of the second solder (Shown as 100% using Fig. 2 for both), wherein the protection layer comprises holes that are respectively filled with the first pad and the second pad (Holes in 105 filled with 106 in Fig. 2), and wherein a width of the first pad is the same as a width of the second pad (All have width 102t, as in Fig. 6).
Regarding Claim 12 - Yokoyama further discloses the semiconductor package of claim 11, wherein a width of the second recess is greater than a width of the first recess (103r > 103s, Figs. 2 and 3).
Regarding Claim 13 - Yokoyama further discloses the semiconductor package of claim 11, wherein a volume of the second solder is greater than a volume of the first solder (107r > 107s [0115] and Fig. 13).
Regarding Claim 15 - Yokoyama further discloses the semiconductor package of claim 11, wherein each of the first recess and the second recess has a circular planar shape, a tetragonal planar shape, a polygonal planar shape, or a cross planar shape (circular in Fig. 3).
Regarding Claim 16 - Yokoyama further discloses the semiconductor package of claim 11, wherein a height of the first pad and a height of the second pad are the same (Using Fig. 2 for both [0062]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8-9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (JP 2011176011 A, hereinafter “Yokoyama”), in view of Shibata et al (US 20190006306 A1, hereinafter “Shibata”).
Regarding Claim 6 - Yokoyama discloses all the limitations of claim 1.
Yokoyama fails to disclose a depth of the second recess is greater than a depth of the first recess.
However, Shibata discloses a depth of the second recess (bottom surface of 30a in Fig. 2) is greater than a depth of the first recess (bottom surface of 30c in Fig. 2)(Adjusted by insulating layers, Shibata [0050] and Fig. 2).
Shibata discloses a group of differently sized solder connections similar to Yokoyama. Shibata teaches the depth of the second recess is greater than the depth of the first recess for the benefits of preventing poor connection and improving reliability (Shibata [0051]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yokoyama and Shibata to make the second recess deeper than the first recess for the benefits of preventing poor connection and improving reliability.
Regarding Claim 8 - Yokoyama discloses all the limitations of claim 1.
Yokoyama fails to disclose a third pad on the first substrate; and a third solder on and coupled to the third pad, wherein the first substrate further comprises an intermediate area between the central area and the peripheral area, wherein the third pad is in the central area, wherein the third pad has a third recess from a top surface of the third pad, wherein a width of the third recess is greater than the width of the first recess and is smaller than the width of the second recess in the first direction.
However, Shibata discloses a third pad on the first substrate (Third Pad in annotated Shibata Fig. 2); and a third solder on and coupled to the third pad (32b. Shibata [0046] and Fig. 2), wherein the first substrate further comprises an intermediate area between the central area and the peripheral area (Third solder between first (32c) and second (32a) solders in Shibata Fig. 2), wherein the third pad is in the intermediate area (Shown between smallest and largest bumps in Fig. 2), wherein the third pad has a third recess from a top surface of the third pad (Third Recess in annotated Shibata Fig. 2), wherein a width of the third recess is greater than the width of the first recess and is smaller than the width of the second recess in the first direction (Width of Third Recess is between the widths of the recesses for first and second recesses, Shibata Fig. 2).
Shibata discloses a group of differently sized solder connections similar to Yokoyama. Shibata teaches a third solder on a third, intermediate sized recess (area and depth) in an intermediate area on the chip for the benefit of keeping the solder height substantially the same across a semiconductor chip (Shibata [0008]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yokoyama and Shibata to use a third solder on a third, intermediate sized recess (area and depth) in an intermediate area on the chip for the benefit of keeping the solder height substantially the same across a semiconductor chip.
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Regarding Claim 9 - Yokoyama modified by Shibata discloses all the limitations of claim 8.
The combination of Yokoyama and Shibata further discloses a volume of the third solder is greater than the volume of the first solder and is less than the volume of the second solder (intermediate area covered by solder 32b with intermediate depth, as shown in Shibata Fig. 2).
Regarding Claim 17 - Yokoyama discloses all the limitations of claim 11.
Yokoyama fails to disclose a depth of the second recess is greater than a depth of the first recess.
However, Shibata discloses a depth of the second recess (bottom surface of 30a in Fig. 2) is greater than a depth of the first recess (bottom surface of 30c in Fig. 2)(Adjusted by insulating layers, Shibata [0050] and Fig. 2).
Shibata discloses a group of differently sized solder connections similar to Yokoyama. Shibata teaches the depth of the second recess is greater than the depth of the first recess for the benefits of preventing poor connection and improving reliability (Shibata [0051]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yokoyama and Shibata to make the second recess deeper than the first recess for the benefits of preventing poor connection and improving reliability.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (JP 2011176011 A, hereinafter “Yokoyama”), in view of Suen et al (US 20150097286 A1, hereinafter “Suen”).
Regarding Claim 18 - Yokoyama discloses a semiconductor package comprising: a first substrate (101 [0059] and Fig. 3); a protection layer on the semiconductor chip (105 [0075] and Fig. 2); a plurality of first pads on the protection layer, the first pads penetrating the protection layer and being directly attached to the first substrate (combination of 102 and 106 [0062] and Fig. 2, in central of annotated Fig. 3); a second substrate on the first substrate (110 [0062] and Fig. 2); a plurality of second pads directly attached to the second substrate (109 [0062] and Fig. 2); and a plurality of solders that respectively connect the plurality of first pads to the plurality of second pads (107 [0062] and Fig. 2 in central and peripheral, annotated Fig. 3), wherein the plurality of first pads have recesses from top surfaces of the first pads (103hs and 103hr [0062] and Fig. 2), wherein widths of the recesses increase in a direction from a center of the first substrate toward an outer lateral surface of the first substrate (103r > 103s Figs. 2 and 3), wherein the protection layer comprises holes that are respectively filled with the first pads (Holes in 105 filled with 106 in Fig. 2), and wherein widths of the first pads are the same as widths of the second pads (All have width 102t, as in Fig. 6).
Yokoyama fails to disclose heights of the plurality of solders increase in the direction from the center of the first substrate toward the outer lateral surface of the first substrate.
However, Suen discloses heights of the plurality of solders increase in the direction from the center of the first substrate toward the outer lateral surface of the first substrate (Suen [0069] and Fig. 6).
Suen discloses an array of solder balls similar to Yokoyama. Sen teaches increasing the height from the center of the substrate for the benefit of improved bonding and durability (Suen [0006]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yokoyama and Suen to increase the height from the center of the substrate for the benefit of improved bonding and durability.
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Regarding Claim 20 - Yokoyama modified by Suen discloses all the limitations of claim 18.
The combination of Yokoyama and Suen further discloses volumes of the solders increase in the direction from the center of the first substrate to the outer lateral surface of the first substrate (107r larger than 107s [0115] and Fig. 13).
Response to Arguments
The applicant argues the 35 U.S.C. 112(a) rejection of claims 2, 14, and 19 by simply restating the specification language, which reads in part “A distance from the lateral surfaces of the first pads 120 (or second pads 130) to the first recesses RS1 (or second recesses RS2) may be in a range of about 2 micrometers to about 5 micrometers.” The examiner respectfully points out that the specification (including the drawings) does not define lateral surfaces of any pads, leaving the measurement location of the referenced distance unclear. The only defined lateral surface is that of the substrate, 100s, mentioned in paragraphs [0064] and [0066], and shown in Fig. 8, of the instant application. Therefore, the 112(a) rejection of claims 2, 14, and 19 remains due to claim limitations referencing distances from undefined lateral surfaces to recesses.
The applicant has added language to claims 1, 11, and 18 specifying the inclusion of a protection layer on the first substrate, direct attachment of pads to substrates, and pad widths, all of which are addressed in the paragraphs above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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