DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-4, 6, 10-11, and 18-20 are rejected under 35 U.S.C. 103 as obvious over Singh et al. (US 2016/0130136 A1), hereinafter as S1, in view of Ehlers (US 2022/0392818 A1), hereinafter as E1
4. Regarding Claim 1, S1 discloses a semiconductor device (see Fig. 1 and [0010] “semiconductor IC die”), comprising:
a semiconductor element (element 152, see [0015] “electronic devices (circuits) 150, 152 (e.g., implemented in the form of IC dies)”) on a substrate (element 111, see [0014] “substrate 111”), a first surface (top surface) of the semiconductor element facing away from the substrate and a second surface (bottom surface) facing the substrate;
a first surface electrode (circular conductive element connected between element 152 and 170, see [0023] “the connectors 170 may include bond pads and bondwires connected between the electronic devices 150, 152 (e.g., between a sensor circuit IC die and a control IC die)”) on the first surface of the semiconductor element (see Fig. 1);
a bonding wire (element 172, see [0023]) connected to the first surface electrode at a bonding portion (see Fig. 1);
a second sealing member (element 162, see [0022] “fluoropolymers”) covering a portion of the first surface electrode (see Fig. 1); and
a third sealing member (element 180, see [0024] “fluorosilicones”) covering the second sealing member.
S1 does not disclose a first sealing member covering the bonding portion; the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member.
E1 discloses a first sealing member covering the bonding portion (see Fig. 4 element 128, see [0038] “the sealing material 128 is polyimide”, covering the bonding portion between element 126 and element 108, see [0033])
The first sealing member as taught by E1 is incorporated as the first sealing member of S1 (see S1 Fig. 1 incorporated as the interface between element 170 and 152), wherein the combination further discloses the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of E1 with S1 because the combination allows for enhanced bond foot sealing which increases power cycling capabilities for semiconductor dies which can be used with noble metal frontside metallization material, or chips used in various power conversion applications (see E1 [0021]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bond wire connecting interface for another to obtain predictable results (see E1 Fig. 4).
5. Regarding Claim 2, S1, E1 disclose the semiconductor device according to claim 1, wherein the elastic modulus of the first sealing member is higher than the elastic modulus of the second sealing member and the elastic modulus of the third sealing member (the first sealing member comprises polyimide, see E1 [0038], which has a higher elastic modulus material property than the second and third sealing members comprising fluorine based resin and silicone respectively, see S1 [0022, 0024]. Furthermore, the material for the sealing members of the prior art overlaps the material stated by the Applicant to have the elastic modulus relationship).
6. Regarding Claim 3, S1, E1 disclose the semiconductor device according to claim 2, wherein the second sealing member has a higher moisture resistance than the third sealing member (The fluoropolymer has a higher moisture resistance material property than the fluorosilicone; Furthermore, the material for the sealing members of the prior art overlaps the material stated by the Applicant to have the moisture resistance relationship).
7. Regarding Claim 4, S1, E1 disclose the semiconductor device according to claim 3, wherein a thickness of the first sealing member is greater than a diameter of the bonding wire (see S1 Fig. 1).
8. Regarding Claim 6, S1, E1 disclose the semiconductor device according to claim 4, wherein a thickness of the second sealing member is greater than the thickness of the first sealing member (see S1 Fig. 1 and E1 Fig. 4), the second sealing member fully covers the first sealing member (see S1 Fig. 1 and E1 Fig. 4), the third sealing member contacts the second sealing member (see S1 Fig. 1 and E1 Fig. 4), and the third sealing member does not contact the first sealing member (see S1 Fig. 1 and E1 Fig. 4).
9. Regarding Claim 10, S1, E1 disclose the semiconductor device according to claim 1, wherein the first sealing member is a resin (see S1 [0022] “fluropolymers”).
10. Regarding Claim 11, S1, E1 disclose the semiconductor device according to claim 1, wherein the second sealing member covers the first sealing member (see S1 Fig. 1 and E1 Fig. 4).
11. Regarding Claim 18, S1 discloses a method for manufacturing a semiconductor module (see Fig. 1 and [0010] “semiconductor IC die”), the method comprising:
bonding a bonding wire (element 172, see [0023]) to a first surface electrode (circular conductive element connected between element 152 and 170, see [0023] “the connectors 170 may include bond pads and bondwires connected between the electronic devices 150, 152 (e.g., between a sensor circuit IC die and a control IC die)”) on a semiconductor element (element 152, see [0015] “electronic devices (circuits) 150, 152 (e.g., implemented in the form of IC dies)”), the semiconductor element being on a substrate (element 111, see [0014] “substrate 111”), a first surface (top surface) of the semiconductor element facing away from the substrate and a second surface (bottom surface) facing the substrate, the first surface electrode being on the first surface of the semiconductor element (see Fig. 1);
applying a second sealing member (element 162, see [0022] “fluoropolymers”) to cover a portion of the first surface electrode (see Fig. 1); and
applying a third sealing member (element 180, see [0024] “fluorosilicones”) to cover the second sealing member.
S1 does not explicitly disclose applying a first sealing member to cover a bonding portion between the first surface electrode and the bonding wire; the second sealing member to cover a portion of the first surface electrode outside the bonding portion; the third sealing member to cover the first sealing member
E1 discloses applying a first sealing member to cover a bonding portion between the first surface electrode and the bonding wire (see Fig. 4 element 128, see [0038] “the sealing material 128 is polyimide”, covering the bonding portion between element 126 and element 108, see [0033])
The first sealing member as taught by E1 is incorporated as the first sealing member of S1 (see S1 Fig. 1 incorporated as the interface between element 170 and 152), wherein the combination further discloses the second sealing member to cover a portion of the first surface electrode outside the bonding portion; the third sealing member to cover the first sealing member.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of E1 with S1 because the combination allows for enhanced bond foot sealing which increases power cycling capabilities for semiconductor dies which can be used with noble metal frontside metallization material, or chips used in various power conversion applications (see E1 [0021]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bond wire connecting interface for another to obtain predictable results (see E1 Fig. 4).
12. Regarding Claim 19, S1, E1 disclose the method according to claim 18, wherein the elastic modulus of the first sealing member is higher than the elastic modulus of the second sealing member and the elastic modulus of the third sealing member (the first sealing member comprises polyimide, see E1 [0038], which has a higher elastic modulus material property than the second and third sealing members comprising fluorine based resin and silicone respectively, see S1 [0022, 0024]. Furthermore, the material for the sealing members of the prior art overlaps the material stated by the Applicant to have the elastic modulus relationship).
13. Regarding Claim 20, S1, E1 disclose the method according to claim 18, wherein the second sealing member covers the first sealing member (see S1 Fig. 1 and E1 Fig. 4).
14. Claim 5 is rejected under 35 U.S.C. 103 as obvious over Singh et al. (US 2016/0130136 A1), hereinafter as S1, in view of Ehlers (US 2022/0392818 A1), hereinafter as E1, in view of Yamada (US 2023/0335452 A1), hereinafter as Y1, in view of Silverbook et al. (US 2009/0078744 A1), hereinafter as S2
15. Regarding Claim 5, S1, E1 disclose the semiconductor device according to claim 4.
S1, E1 does not disclose wherein a thickness of the second sealing member is less than the thickness of the first sealing member.
Y1 discloses a thickness of a lower sealing member is adjustable at different locations (see Fig. 11 lower sealing member element 27 has smallest thickness at the area of element 27a adjacent to a lower left connection of a bond wire element 26).
The thinnest thickness of the lower sealing member at an area above a first central location adjacent to a lower left connection of a bond wire as taught by Y1 is incorporated as a thinnest thickness of the lower sealing member at an area above a first central location adjacent to a lower left connection of a bond wire of S1, E1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with S1 because the combination allows for decreased stress according to temperature change and mitigates cracks (see Y1 [0104]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known shape of a lower sealing member in a similar device for another to obtain predictable results (see Y1 Fig. 11).
S2 discloses the first sealing member encases the entire bond wire (see Fig. 3C element 2 encases the entire bond wire element 16).
The first sealant size with respect to the bond wire as taught by S2 is incorporated as the first sealant size with respect to the bond wire of S1, E1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S2 with S1 because the combination allows for the first sealant to form a surface that can perform functions other than just encapsulate the wire bonds with a multitude of shapes for a variety of purposes (see S2 [0070]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known size of a first sealant with respect to a bond wire for another to obtain predictable results (see S2 Fig. 3C, and also see Fig. 2 a smaller first sealant can alternatively cover only the bonding area).
The combination of S1, E1, Y1, S2 disclose wherein a thickness of the second sealing member is less than the thickness of the first sealing member (see S1, in light of the combination with Y1 and S2, the second sealing member element 162 of S1 has a smallest thickness above element 150 adjacent to a lower left connection of element 170 and the first sealing member extends to encase the entire bond wire)
16. Claims 1 and 7-9 are rejected under 35 U.S.C. 103 as obvious over Singh et al. (US 2016/0130136 A1), hereinafter as S1, in view of Huang (US 2024/0014155 A1), hereinafter H1
Regarding Claim 1, S1 discloses a semiconductor device (see Fig. 1 and [0010] “semiconductor IC die”), comprising:
a semiconductor element (element 152, see [0015] “electronic devices (circuits) 150, 152 (e.g., implemented in the form of IC dies)”) on a substrate (element 111, see [0014] “substrate 111”), a first surface (top surface) of the semiconductor element facing away from the substrate and a second surface (bottom surface) facing the substrate;
a first surface electrode (circular conductive element connected between element 152 and 170, see [0023] “the connectors 170 may include bond pads and bondwires connected between the electronic devices 150, 152 (e.g., between a sensor circuit IC die and a control IC die)”) on the first surface of the semiconductor element (see Fig. 1);
a bonding wire (element 172, see [0023]) connected to the first surface electrode at a bonding portion (see Fig. 1);
a second sealing member (element 162, see [0022] “fluoropolymers”) covering a portion of the first surface electrode (see Fig. 1); and
a third sealing member (element 180, see [0024] “fluorosilicones”) covering the second sealing member.
S1 does not disclose a first sealing member covering the bonding portion; the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member.
H1 discloses a first sealing member covering the bonding portion (see Fig. 1 element 40, see [0037, 0047] “melting the solder 22 by heating and enabling the solder to enter the wire bonding area 21, so as to form a coating layer 40 wrapping the welding part 31”)
The first sealing member as taught by H1 is incorporated as the first sealing member of S1 (see S1 Fig. 1 incorporated as the interface between element 170 and 152), wherein the combination further discloses the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with S1 because the combination allows for greatly improved bonding quality and reliability (see H1 [0042]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bond wire connecting interface for another to obtain predictable results (see H1 Fig. 1).
Regarding Claim 7, S1, H1 disclose the semiconductor device according to claim 1, wherein the first sealing member is solder (see H1 [0047]).
17. Regarding Claim 8, S1, H1 disclose the semiconductor device according to claim 7, wherein the second sealing member is a first-type resin (see S1 [0022] “fluropolymers”).
18. Regarding Claim 9, S1, H1 disclose the semiconductor device according to claim 8, wherein the third sealing member is a second-type resin different from the first-type resin (see S1 [0024] “fluorosilicones”).
19. Claims 12-15 and 17 are rejected under 35 U.S.C. 103 as obvious over Singh et al. (US 2016/0130136 A1), hereinafter as S1, in view of Ehlers (US 2022/0392818 A1), hereinafter as E1, in view of Koga et al. (US 2007/0284745 A1), hereinafter as K1
20. Regarding Claim 12, S1 disclose a semiconductor module (see Fig. 1 and [0010] “semiconductor IC die”), comprising:
a housing (element 110, see [0012] “package housing 110”); and
a semiconductor device (comprising element 152, see [0015] “electronic devices (circuits) 150, 152 (e.g., implemented in the form of IC dies)”) below the housing, the semiconductor device includes:
a semiconductor element (element 152) on a substrate (element 111, see [0014] “substrate 111”), a first surface (top surface) of the semiconductor element facing away from the substrate and a second surface (bottom surface) facing the substrate;
a first surface electrode (circular conductive element connected between element 152 and 170, see [0023] “the connectors 170 may include bond pads and bondwires connected between the electronic devices 150, 152 (e.g., between a sensor circuit IC die and a control IC die)”) on the first surface of the semiconductor element (see Fig. 1);
a bonding wire (element 172, see [0023]) connected to the first surface electrode at a bonding portion (see Fig. 1);
a second sealing member (element 162, see [0022] “fluoropolymers”) covering a portion of the first surface electrode (see Fig. 1); and
a third sealing member (element 180, see [0024] “fluorosilicones”) covering the second sealing member (see Fig. 1).
S1 does not disclose the substrate is in the housing; a first sealing member covering the bonding portion; the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member.
K1 discloses the substrate is in the housing (see Figs. 1A-B housing element 8 and substrate element 1 within the housing, see [0020] “substrate 1”, [0022] “casing 8”)
The substrate location in the housing as taught by K1 is incorporated as the substrate location in the housing of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with S1 because the combination provides a fitted with the substrate without an intermediate adhesive (see K1 [0026]), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known substrate location with respect to the housing another in a similar packaging device to obtain predictable results (see K1 Figs. 1A-B).
S1, K1 do not disclose a first sealing member covering the bonding portion; the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member
E1 discloses a first sealing member covering the bonding portion (see Fig. 4 element 128, see [0038] “the sealing material 128 is polyimide”, covering the bonding portion between element 126 and element 108, see [0033])
The first sealing member as taught by E1 is incorporated as the first sealing member of S1 (see S1 Fig. 1 incorporated as the interface between element 170 and 152), wherein the combination further discloses the second sealing member covering a portion of the first surface electrode outside the bonding portion; the third sealing member covering the first sealing member.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of E1 with S1, K1 because the combination allows for enhanced bond foot sealing which increases power cycling capabilities for semiconductor dies which can be used with noble metal frontside metallization material, or chips used in various power conversion applications (see E1 [0021]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bond wire connecting interface for another to obtain predictable results (see E1 Fig. 4).
21. Regarding Claim 13, S1, K1, E1 disclose the semiconductor module according to claim 12, wherein the elastic modulus of the first sealing member is higher than the elastic modulus of the second sealing member and the elastic modulus of the third sealing member (the first sealing member comprises polyimide, see E1 [0038], which has a higher elastic modulus material property than the second and third sealing members comprising fluorine based resin and silicone respectively, see S1 [0022, 0024]. Furthermore, the material for the sealing members of the prior art overlaps the material stated by the Applicant to have the elastic modulus relationship).
22. Regarding Claim 14, S1, K1, E1 disclose the semiconductor module according to claim 13, wherein the second sealing member has a higher moisture resistance than the third sealing member (The fluoropolymer has a higher moisture resistance material property than the fluorosilicone; Furthermore, the material for the sealing members of the prior art overlaps the material stated by the Applicant to have the moisture resistance relationship)..
23. Regarding Claim 15, S1, K1, E1 disclose the semiconductor module according to claim 14, wherein a thickness of the first sealing member is greater than a diameter of the bonding wire (see S1 Fig. 1).
24. Regarding Claim 17, S1, K1, E1 disclose the semiconductor module according to claim 15, wherein
a thickness of the second sealing member is greater than the thickness of the first sealing member (see S1 Fig. 1 and E1 Fig. 4),
the second sealing member fully covers the first sealing member (see S1 Fig. 1 and E1 Fig. 4), the third sealing member contacts the second sealing member (see S1 Fig. 1 and E1 Fig. 4), and
the third sealing member does not contact the first sealing member (see S1 Fig. 1 and E1 Fig. 4).
25. Claim 16 is rejected under 35 U.S.C. 103 as obvious over Singh et al. (US 2016/0130136 A1), hereinafter as S1, in view of Ehlers (US 2022/0392818 A1), hereinafter as E1, in view of Koga et al. (US 2007/0284745 A1), hereinafter as K1, in view of Yamada (US 2023/0335452 A1), hereinafter as Y1, in view of Silverbook et al. (US 2009/0078744 A1), hereinafter as S2
26. Regarding Claim 16, S1, K1, E1 disclose the semiconductor module according to claim 15.
S1, K1, E1 do not disclose wherein a thickness of the second sealing member is less than the thickness of the first sealing member.
Y1 discloses a thickness of a lower sealing member is adjustable at different locations (see Fig. 11 lower sealing member element 27 has smallest thickness at the area of element 27a adjacent to a lower left connection of a bond wire element 26).
The thinnest thickness of the lower sealing member at an area above a first central location adjacent to a lower left connection of a bond wire as taught by Y1 is incorporated as a thinnest thickness of the lower sealing member at an area above a first central location adjacent to a lower left connection of a bond wire of S1, K1, E1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with S1 because the combination allows for decreased stress according to temperature change and mitigates cracks (see Y1 [0104]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known shape of a lower sealing member in a similar device for another to obtain predictable results (see Y1 Fig. 11).
S2 discloses the first sealing member encases the entire bond wire (see Fig. 3C element 2 encases the entire bond wire element 16).
The first sealant size with respect to the bond wire as taught by S2 is incorporated as the first sealant size with respect to the bond wire of S1, K1, E1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S2 with S1 because the combination allows for the first sealant to form a surface that can perform functions other than just encapsulate the wire bonds with a multitude of shapes for a variety of purposes (see S2 [0070]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known size of a first sealant with respect to a bond wire for another to obtain predictable results (see S2 Fig. 3C, and also see Fig. 2 a smaller first sealant can alternatively cover only the bonding area).
The combination of S1, K1, E1, Y1, S2 disclose wherein a thickness of the second sealing member is less than the thickness of the first sealing member (see S1, in light of the combination with Y1 and S2, the second sealing member element 162 of S1 has a smallest thickness above element 150 adjacent to a lower left connection of element 170 and the first sealing member extends to encase the entire bond wire)
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818
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