DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-6, 16-20 in the reply filed on 15 January 2026 is acknowledged.
Claims 1-6, 16-20 are pending in the application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “…a layer of tungsten nitride that is below the titanium nitride…” as recited in claim 2, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 16-20 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Fayrushin et al (US 10,923,493 B2 hereinafter “Fayrushin”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Fayrushin, for example in Figs. 1-4, discloses an apparatus (e.g., 200; in Fig. 2E related in Figs. 1-2A, 2B, 2C, 2D, 3-4), comprising:
a pillar of poly material (e.g., vertical component between 106 and 108 on both side; in Fig. 1A related in Figs. 1B-1F, 2A-2E, 3-4) disposed vertically through a stack of materials (e.g., conductive material 106 and dielectric material 108; in Fig. 1A related in Figs. 1B-1F, 2A-2E, 3-4) comprising conductive tiers (e.g., a plurality of 106; related in Figs. 1B-1F, 2A-2E, 3-4) and dielectric tiers (e.g., a plurality of 108; related in Figs. 1B-1F, 2A-2E, 3-4), wherein the conductive tiers comprise word lines (e.g., conductive gate materials; related in Figs. 1B-1F, 2A-2E, 3-4) for a memory array (within Fig. 3 related in Figs. 1-2, 4);
a concave liner (e.g., layer 125; in Fig. 1B related in Figs. 1A, 1C-1F, 2-4) comprising a first conductive material (e.g., a band offset material; in Fig. 1B related in Figs. 1A, 1C-1F, 2-4) and disposed within the pillar (see for example in Fig. 1B related in Figs. 1A, 1C-1F, 2-4);
a second conductive material (e.g., a top plug material 124; in Fig. 1D related in Figs. 1A, 1B, 1E-1F, 2-4) that at least partially fills a void formed by the concave liner (see for example in Fig. 1D related in Figs. 1A, 1B, 1E-1F, 2-4); and
a conductive pillar in contact with the second conductive material, wherein the conductive pillar comprises a bit line contact for a bit line of the memory array (e.g., 126, 226, 326; in Figs. 1-3 related in Fig. 4).
Regarding claim 2, Fayrushin, for example in Figs. 1-9, discloses wherein the second conductive material comprises titanium nitride (e.g., implied that conductive material as titanium nitride TiN, tungsten nitride WN may be deposited within the gaps; in Figs. 1-2 related in Figs. 3-4), the apparatus further comprising: a layer of tungsten nitride that is below the titanium nitride and that at least partially fills the concave liner (e.g., implied that may be utilized in any such memory devices including similar materials as tungsten nitride WN and process; in Figs. 1-2 related in Figs. 3-4, as discussed above).
Regarding claim 3, Fayrushin, for example in Figs. 1-4, discloses wherein the second conductive material comprises tungsten (e.g., implied that may be utilized in any such memory device including similar material as tungsten W; in Figs. 1-2 related in Figs. 3-4), the apparatus further comprising: an oxide material that at least partially surrounds the pillar of poly material and that at least partially surrounds the conductive pillar (e.g., implied that layer 112/116 surrounds the conductive pillar; in Figs. 1-3 related in Fig. 4, as discussed above).
Regarding claim 4, Fayrushin, for example in Figs. 1-4, discloses further comprising: a layer of silicon oxycarbonitride (SiOCN) disposed over the second conductive material, wherein the conductive pillar extends through the layer of SiOCN (e.g., implied that silicon with native oxide or a carbon-containing silicon nitride; in Figs. 1-2 related in Figs. 3-4, as discussed above).
Regarding claim 5, Fayrushin, for example in Figs. 1-4, discloses wherein the conductive pillar comprises a third conductive material at least partially surrounded by a fourth conductive material (see for example in Figs. 1-3 related in Fig. 4, as discussed above).
Regarding claim 6, Fayrushin, for example in Figs. 1-4, discloses wherein the third conductive material comprises tungsten and the fourth conductive material comprises titanium nitride (e.g., implied that may be utilized in any such memory device including similar material as titanium nitride TiN; in Figs. 1-2 related in Figs. 3-4, as discussed above).
Regarding Independent Claim 16, Fayrushin, for example in Figs. 1-4, discloses an apparatus (e.g., 200; in Fig. 2E related in Figs. 1-2A, 2B, 2C, 2D, 3-4), comprising: a pillar of poly material (e.g., vertical component between 106 and 108 on both side; in Fig. 1A related in Figs. 1B-1F, 2A-2E, 3-4) disposed vertically through a stack of materials (e.g., conductive material 106 and dielectric material 108; in Fig. 1A related in Figs. 1B-1F, 2A-2E, 3-4) comprising conductive tiers that comprise word lines (e.g., conductive gate materials; related in Figs. 1B-1F, 2A-2E, 3-4) for a memory array (see for example in Fig. 3 related in Figs. 1-2, 4); an oxide material that at least partially surrounds the pillar of poly material (e.g., implied that layer 112/116 surrounds the conductive pillar; in Figs. 1-3 related in Fig. 4, as discussed above); a first conductive material that is disposed within the pillar and is at least partially surrounded by the oxide material (e.g., a band offset material; in Fig. 1B related in Figs. 1A, 1C-1F, 2-4); a second conductive material disposed within the first conductive material (e.g., a top plug material 124; in Fig. 1D related in Figs. 1A, 1B, 1E-1F, 2-4); and a bit line contact for a bit line of the memory array in contact with the second conductive material (e.g., 126, 226, 326; in Figs. 1-3 related in Fig. 4).
Regarding claim 17, Fayrushin, for example in Figs. 1-4, discloses wherein the first conductive material comprises a titanium alloy and the second conductive material comprises titanium nitride, the apparatus further comprising: tungsten nitride disposed between the titanium alloy and the titanium nitride (e.g., implied that may be utilized in any such memory device including similar material as titanium nitride TiN; in Figs. 1-2 related in Figs. 3-4, as discussed above).
Regarding claim 18, Fayrushin, for example in Figs. 1-4, discloses wherein the first conductive material comprises a titanium nitride and the second conductive material comprises tungsten (e.g., implied that may be utilized in any such memory device including similar material as tungsten W; in Figs. 1-2 related in Figs. 3-4, as discussed above).
Regarding claim 19, Fayrushin, for example in Figs. 1-4, discloses further comprising: a layer of silicon oxycarbonitride (SiOCN) disposed within the oxide material and above the first conductive material (e.g., implied that silicon with native oxide or a carbon-containing silicon nitride; in Figs. 1-2 related in Figs. 3-4, as discussed above), the second conductive material, and the conductive tiers, wherein the bit line contact extends through the layer of SiOCN to contact the second conductive material (e.g., implied that silicon with native oxide or a carbon-containing silicon nitride; in Figs. 1-2 related in Figs. 3-4, as discussed above).
Regarding claim 20, Fayrushin, for example in Figs. 1-4, discloses wherein the bit line contact comprises a conductive pillar comprising a third conductive material that is separated from the second conductive material by a fourth conductive material (see for example in Figs. 1-2 related in Figs. 3-4, as discussed above), the apparatus further comprising: dielectric tiers disposed in between the conductive tiers and at least partially surrounding the pillar of poly material (e.g., layer 128/228; in Figs. 1E, 1F, 2E related in Figs. 1A, 1B, 1C, 1D, 2A, 2B, 2C, 2D, 3-4, as discussed above).
Conclusion
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/THA-O H BUI/ Primary Examiner, Art Unit 2825 03/29/2026