DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 7/28/2026 is acknowledged.
Claim Objections
Claim 12 objected to because of the following informalities: the claim appears to have a typographical error, " the semiconductor device of claim 10, wherein the power via". For the purpose of examination, the examiner will interpret the above limitation as " the semiconductor device of claim 10, wherein a power via". Appropriate correction is required.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/17/2024 and 8/14/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. US 2024/0112984.
Re claim 1, Li teaches a semiconductor device (fig1 and 2), comprising:
at least one field-effect transistor (FET) (T1, T2, fig1 and 2C, [52]) on a frontside of a wafer (top side of 100 facing 155, fig1 and 2A-D, [52, 53]);
a backside power rail (120, fig1 and 2A-D, [52]) on a backside of the wafer (side of 100 with 120, fig1 and 2A-D, [52]); and
a backside power bar (125, fig1 and 2A-D, [52]) connecting the backside power rail (120, fig1 and 2A-D, [52]) to a source/drain region (252, fig2B and 2D, [55]) of the at least one FET from the frontside of the wafer (CA 247 contact S/D 252 from front side of wafer, fig2B and 2D, [55]) and a gate (135, fig2C, [54]) of the at least one FET from the backside of the wafer (125 connected to 135 from back side of wafer, fig2C, [55]).
Re claim 2, Li teaches the semiconductor device of claim 1, further comprising: a power via (VBPR 233, fig2D, [54]); and a middle-of-line source/drain contact (CA 247, fig2D, [55]) in direct contact with the power via (VBPR 233, fig2D, [54]), wherein the backside power bar (125, fig1 and 2A-D, [52]) is connected to the source/drain region (252, fig2B and 2D, [55]) through the power via (VBPR 233, fig2D, [54]) and the middle-of-line source/drain contact (CA 247, fig2D, [55] ).
Re claim 5, Li teaches the semiconductor device of claim 1, wherein the backside power bar (125, fig1 and 2A-D, [52]) directly contacts the gate (135, fig2C, [54]).
Re claim 6, Li teaches the semiconductor device of claim 1, wherein the backside power bar (125, fig1 and 2A-D, [52]) directly contacts a portion of a sidewall of the gate (sidewall of 135 in contact with 125, fig2C).
Re claim 9, Li teaches the semiconductor device of claim 1, wherein the at least one FET further (T1, T2, fig1 and 2C, [52]) comprises a stack of active layers (241, fig2B and 2C, [55]) which serve as a channel ([55]), and wherein the gate (135, fig2C, [54]) surrounds a portion of each of the active layers in a gate-all-around configuration (fig2B and 2C).
Claim(s) 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. US 2023/0086033.
Re claim 10, Xie teaches a semiconductor device (fig11E), comprising:
at least a first field-effect transistor (FET) (FET above 105, fig11E, [40]) and a second FET (FET under 105, fig11E, [40]) on a frontside of a wafer (top side of wafer facing 132, fig12A-D, [57]), wherein the first FET and the second FET each comprises a channel (112, fig12D, [40]), a gate (126, fig12D, [56]) on the channel, and source/drain regions (122, fig12B, [54]) on opposite ends of the channel;
a backside power rail (part of 138 above 105, fig12B-D, [60]) on a backside of the wafer (side of wafer with 105, fig15E, [40]); and
a backside power bar (105, fig11E and 12A-D, [40]) present between the first FET and the second FET (FET located above and under 105, fig11E, [40]), wherein the backside power bar (105, fig11E and 12A-D, [40]) connects the backside power rail (part of 138 above 105, fig12B-D, [60]) to a given one of the source/drain regions (122, fig12B , [59]) of the first FET from the frontside of the wafer (130 contact S/D 122 from front side of wafer, fig12B, [57]) and the gate (126, fig12D, [57]) of the first FET from the backside of the wafer (105 connected to 126 via 138, fig12D, [57, 60]).
Re claim 11, Xie teaches the semiconductor device of claim 10, further comprising: a power via (part of 130 between 122, fig12B, [57]); and a middle-of-line source/drain contact (part of 130 between 122 and 132 fig12B, [57]) in direct contact with the power via (part of 130 between 122, fig12B, [57]), wherein the backside power bar (105, fig11E and 12A-D, [40]) is connected to the given one of the source/drain region regions (122, fig12B, [57]) of the first FET through the power via (part of 130 between 122, fig12B, [57]) and the middle-of-line source/drain contact (part of 130 between 122 and 132 fig12B, [57]).
Re claim 12, Xie teaches the semiconductor device of claim 10, whereina power via (part of 130 between 122, fig12B, [57]) is offset from the source/drain region (122 right, fig12B , [59]) of the first FET and the source/drain region (122 right , fig12B , [59]) of the second FET by a dielectric material (124 and 116, fig12B, [55]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. US 2023/0086033 and Li et al. US 2024/0112984.
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Re claim 13, Xie does not explicitly show the semiconductor device of claim 10, wherein the backside power bar directly contacts the gate.
Xie teaches a semiconductor device (fig11E), comprising: at least a first field-effect transistor (FET) (FET above 105, fig11E, [40]) and a second FET (FET under 105, fig11E, [40]) on a frontside of a wafer (top side of wafer facing 132, fig12A-D, [57]), a backside power bar (105, fig11E and 12A-D, [40]) present between the first FET and the second FET (FET located above and under 105, fig11E, [40]), wherein the backside power bar (105, fig11E and 12A-D, [40]) connects the backside power rail (part of 138 above 105, fig12B-D, [60]) to a given one of the source/drain regions (122, fig12B , [59]) of the first FET from the frontside of the wafer (130 contact S/D 122 from front side of wafer, fig12B, [57]) and the gate (126, fig12D, [57]) of the first FET from the backside of the wafer (105 connected to 126 via 138, fig12D, [57, 60]).
Li teaches a backside power rail (120, fig1 and 2A-D, [52]) on a backside of the wafer (side of 100 with 120, fig1 and 2A-D, [52]); and a backside power bar (125, fig1 and 2A-D, [52]) present between the first FET and the second FET (T1, T2, fig1 and 2C, [52]), wherein the backside power bar (125, fig1 and 2A-D, [52]) connects the backside power rail (120, fig1 and 2A-D, [52]) to a given one of the source/drain regions (252, fig2B and 2D, [55]) of the first FET from the frontside of the wafer (CA 247 contact S/D 252 from front side of wafer, fig2B and 2D, [55]) and the gate (140, fig2C, [54]) of the second FET from the backside of the wafer (125 connected to 140, fig2C, [55]), wherein the backside power bar (125, fig1 and 2A-D, [52]) directly contacts the gate (140, fig2C, [54]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie and Li to form the circuit shown in Xie fig11E by moving Li 130 VBPR (fig2C and 11C) to contact T2 140 and form both VBPR for gate and VBPR for S/D on same side as in Xie fig11E. The motivation to do so is to form a compact Gate tie-down with enhanced device performance and minimal loss of area (Li, [50]).
Re claim 14, Xie does not explicitly show the semiconductor device of claim 10, wherein the backside power bar directly contacts a portion of a sidewall of the gate of the first FET.
Xie teaches a semiconductor device (fig11E), comprising: at least a first field-effect transistor (FET) (FET above 105, fig11E, [40]) and a second FET (FET under 105, fig11E, [40]) on a frontside of a wafer (top side of wafer facing 132, fig12A-D, [57]), a backside power bar (105, fig11E and 12A-D, [40]) present between the first FET and the second FET (FET located above and under 105, fig11E, [40]), wherein the backside power bar (105, fig11E and 12A-D, [40]) connects the backside power rail (part of 138 above 105, fig12B-D, [60]) to a given one of the source/drain regions (122, fig12B , [59]) of the first FET from the frontside of the wafer (130 contact S/D 122 from front side of wafer, fig12B, [57]) and the gate (126, fig12D, [57]) of the first FET from the backside of the wafer (105 connected to 126 via 138, fig12D, [57, 60]).
Li teaches a backside power rail (120, fig1 and 2A-D, [52]) on a backside of the wafer (side of 100 with 120, fig1 and 2A-D, [52]); and a backside power bar (125, fig1 and 2A-D, [52]) present between the first FET and the second FET (T1, T2, fig1 and 2C, [52]), wherein the backside power bar (125, fig1 and 2A-D, [52]) connects the backside power rail (120, fig1 and 2A-D, [52]) to a given one of the source/drain regions (252, fig2B and 2D, [55]) of the first FET from the frontside of the wafer (CA 247 contact S/D 252 from front side of wafer, fig2B and 2D, [55]) and the gate (140, fig2C, [54]) of the second FET from the backside of the wafer (125 connected to 140, fig2C, [55]), wherein the backside power bar (125, fig1 and 2A-D, [52]) directly contacts the gate (140, fig2C, [54]), wherein the backside power bar (125, fig1 and 2A-D, [52]) directly contacts a portion of a sidewall of the gate of the FET (sidewall of 140 in contact with 125, fig2C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie and Li to form the circuit shown in Xie fig11E by moving Li 130 VBPR (fig2C and 11C) to contact T2 140 and form both VBPR for gate and VBPR for S/D on same side as in Xie fig11E. The motivation to do so is to form a compact Gate tie-down with enhanced device performance and minimal loss of area (Li, [50]).
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. US 2024/0112984 in view of Chang et al. US 2020/0294860.
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Re claim 3, Li does not explicitly show the semiconductor device of claim 2, wherein the power via is offset from the source/drain region by a layer of a dielectric material.
Chang teaches wherein the power via (part of 140 in contact with 122, fig1F and 2L, [54]) is offset from the source/drain region (138/130, fig2L, [45]) by a layer of a dielectric material (128 and 132 between 130 and 140, fig2I, [38, 41, 45]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Li and Chang to replace 233 and 252 of Li with 140 and 130/138 of Chang with 132 and 128 between 130 and 140. The motivation to do so is to provide enough stress to enhance carrier mobility and reduce resistance of the contact structure (Chang, [40, 61]).
Re claim 4, Li modified above teaches the semiconductor device of claim 3, wherein the dielectric material comprises a nitride dielectric material (128 and 132 as nitrides between 130 and 140, fig2I, [38, 41, 45]).
Allowable Subject Matter
Claim 7-8 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to reduce size of the high voltage transistor and increase the breakdown voltage of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
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/XIAOMING LIU/Examiner, Art Unit 2812
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