DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 21.
Pending: 1-5 and 11-25.
Canceled: 6-10.
New: 21-25.
Withdrawn: 14, 15 and 17
Information Disclosure Statement
Applicant’s IDS(s) submitted on 4/10/2024, 6/10/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant’s election without traverse of in invention II species IV claims 1-5, 11-13, 16, 18-25, the reply filed on 7/27/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, in claim 16, 18 and 22 require to have “contact via structure” including “annular horizontal surface” in Applicant specification paragraph [0093] describe “the upper portion has a greater lateral extent than the downward-protruding portion, and the horizontal surface comprises an annular bottom surface of the upper portion of a respective contact via structure 180 as illustrated in FIGS. 16, 17A, and 17B.” however Examiner do not see the contact via structure with circinate or ringed horizontal surface, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 11-12, 16, 18-19, 21-22 and 25 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Chang et al., US PG pub. 20190067559 A1.
Re: Independent Claim 1, Chang discloses depositing a layer stack (802,804,806, fig. 8;124, fig. 16) including a bottom electrode (802, fig. 8) material layer, memory material layers (804, fig. 8), a top electrode (806, fig. 8;124, fig. 16) material layer, and a metallic etch mask (814, fig. 8-14) material layer over a substrate (102, fig. 4);
patterning the layer stack (802,804,806, fig. 8;124, fig. 16) into an array of memory cells and an array of metallic etch mask (814, fig. 8-14) portions, wherein each of the memory cells comprises a bottom electrode (802, fig. 8), a memory material stack (122, fig.9), and a top electrode (806, fig. 8;124, fig. 16), and each of the metallic etch mask (814, fig. 8-14) portions is a patterned portion (814, fig. 9) of the metallic etch mask (814, fig. 8-14) material layer that overlies a respective one of the memory cells;
depositing a via-level dielectric layer (142, fig. 14) over the array of metallic etch mask (814, fig. 8-14) portions;
etching an array of via cavities (1506, fig. 15; ¶0048) through the via-level dielectric layer (142, fig. 14), wherein top surfaces of the metallic etch mask (814, fig. 8-14) portions are physically exposed underneath the array of via cavities (1506, fig. 15; ¶0048);
removing (fig. 16) the array of metallic etch mask (814, fig. 8-14) portions, wherein top surfaces of the top electrode (806, fig. 8;124, fig. 16)s are physically exposed underneath the array of via cavities (1506, fig. 15; ¶0048); and
forming an array of contact via structure (140, fig. 18)s on the top surfaces of the top electrode (806, fig. 8;124, fig. 16)s in the array of via cavities (1506, fig. 15; ¶0048).
Re: Claim 4, Chang disclose(s) all the limitations of claim 1 on which this claim depends. Chang further discloses: forming a dielectric spacer (1002, fig. 10) around each metallic etch mask (814, fig. 8-14) portion of the array of metallic etch mask (814, fig. 8-14) portions;
forming at least one dielectric etch stop layer (1502, fig. 15) above the dielectric spacer (1002, fig. 10)s and the array of metallic etch mask (814, fig. 8-14) portions, wherein the via-level dielectric layer (142, fig. 14) is formed above the at least one dielectric etch stop layer (1502, fig. 15); and
extending the array of via cavities (1506, fig. 15; ¶0048) through the at least one dielectric etch stop layer (1502, fig. 15) by performing at least one etch process,
wherein an inner sidewall of a respective dielectric spacer (1002, fig. 10) is physically exposed upon removal of the array of metallic etch mask (814, fig. 8-14) portions.
Re: Claim 5, Chang disclose(s) all the limitations of claim 1 on which this claim depends. Chang further discloses: the memory material layers (804, fig. 8) comprise a layer stack (802,804,806, fig. 8;124, fig. 16) including a synthetic antiferromagnet layer, a nonmagnetic tunnel barrier layer (128, fig. 16), and a free magnetization layer (130, fig. 16); and
each of the memory cells comprises a vertical stack including a synthetic antiferromagnet structure (126, fig. 16), a nonmagnetic tunnel barrier layer (128, fig. 16), and a free magnetization layer (130, fig. 16).
Re: Independent Claim 11, Chang discloses depositing a layer stack (802,804,806, fig. 8;124, fig. 16) including a bottom electrode (802, fig. 8) material layer, memory material layers (804, fig. 8), a top electrode (806, fig. 8;124, fig. 16) material layer, and a metallic etch mask (814, fig. 8-14) material layer over a substrate (102, fig. 4);
patterning the layer stack (802,804,806, fig. 8;124, fig. 16) into an array of memory cells and an array of metallic etch mask (814, fig. 8-14) portions, wherein each of the memory cells comprises a bottom electrode (802, fig. 8), a memory material stack (122, fig.9), and a top electrode (806, fig. 8;124, fig. 16), and each of the metallic etch mask (814, fig. 8-14) portions is a patterned portion (814, fig. 9) of the metallic etch mask (814, fig. 8-14) material layer that overlies a respective one of the memory cells;
forming a memory-level dielectric layer (118, fig. 14), at least dielectric etch stop layer (1502, fig. 15), and a via-level dielectric layer (142, fig. 14); and
forming an array of contact via structure (140, fig. 18)s through the via-level dielectric layer (142, fig. 14) and the at least one dielectric etch stop layer (1502, fig. 15) directly on a top surface of a respective one of the top electrode (806, fig. 8;124, fig. 16)s within the array of memory cells.
Re: Claim 12, Chang disclose(s) all the limitations of claim 11 on which this claim depends. Chang further discloses: forming an array of via cavities (1506, fig. 15; ¶0048) through the via-level dielectric layer (142, fig. 14) and the at least one dielectric etch stop layer (1502, fig. 15); and
removing the array of metallic etch mask (814, fig. 8-14) portions selective to materials of the top electrode (806, fig. 8;124, fig. 16)s, the via-level dielectric layer (142, fig. 14), and the memory-level dielectric layer (118, fig. 14), wherein the array of contact via structure (140, fig. 18)s fills voids that are formed by removal of the array of metallic etch mask (814, fig. 8-14) portions.
Re: Claim 16, Chang disclose(s) all the limitations of claim 12 on which this claim depends. Chang further discloses: a contact via structure (140, fig. 18)s among the array of contact via structure (140, fig. 18)s comprises an annular horizontal surface (¶0027; fig. 1A and 1B); and
the annular horizontal surface (¶0027; fig. 1A and 1B) is adjoined to a bottom periphery of a first sidewall of an upper portion of the contact via structure (140, fig. 18) which is laterally surrounded by the via-level dielectric layer (142, fig. 14) and the at least one dielectric etch stop layer (1502, fig. 15), and is adjoined to a top periphery of a second sidewall of a lower portion of the contact via structure (140, fig. 18) that is laterally surrounded by the memory-level dielectric layer (118, fig. 14).
Re: Claim 18, Chang disclose(s) all the limitations of claim 16 on which this claim depends. Chang further discloses: the bottom periphery of a first sidewall is adjoined to an inner periphery of the annular horizontal surface (¶0027; fig. 1A and 1B); and the top periphery of the second sidewall is adjoined to an outer periphery of the annular horizontal surface (¶0027; fig. 1A and 1B).
Re: Claim 19, Chang disclose(s) all the limitations of claim 11 on which this claim depends. Chang further discloses: forming an array of via cavities (1506, fig. 15; ¶0048) through the via-level dielectric layer (142, fig. 14) by performing an anisotropic etch process (¶0042) selective to the at least one dielectric etch stop layer (1502, fig. 15); and
extending the array of via cavities (1506, fig. 15; ¶0048) through the at least one dielectric etch stop layer (1502, fig. 15) by removing portions of the at least one dielectric etch stop layer (1502, fig. 15) selective to a material of the array of metallic etch mask (814, fig. 8-14) portions.
Re: Independent Claim 21, Chang discloses forming an array of memory cells and an array of metallic etch mask (814, fig. 8-14) portions overlying the array of memory cells over a substrate (102, fig. 4), wherein each of the memory cells comprises a bottom electrode (802, fig. 8), a memory material stack (122, fig.9), and a top electrode (806, fig. 8;124, fig. 16);
forming a dielectric spacer (1002, fig. 10) around each metallic etch mask (814, fig. 8-14) portion of the array of metallic etch mask (814, fig. 8-14) portions;
forming a memory-level dielectric layer (118, fig. 14) embedding the dielectric spacer (1002, fig. 10)s and the array of memory cells;
forming at least one dielectric etch stop layer (1502, fig. 15) and a via-level dielectric layer (142, fig. 14) over the memory-level dielectric layer (118, fig. 14);
forming an array of via cavities (1506, fig. 15; ¶0048) through the via-level dielectric layer (142, fig. 14) and the at least one dielectric etch stop layer (1502, fig. 15) such that top surfaces of the metallic etch mask (814, fig. 8-14) portions are physically exposed underneath the array of via cavities (1506, fig. 15; ¶0048);
removing the array of metallic etch mask (814, fig. 8-14) portions selective to materials of the top electrode (806, fig. 8;124, fig. 16)s, whereby each via cavity is expanded to include an upper portion and a downward- protruding portion that has a greater lateral extent than the upper portion, and an inner sidewall of a respective dielectric spacer (1002, fig. 10) is physically exposed; and
forming an array of contact via structure (140, fig. 18)s in the expanded via cavities (1506, fig. 15; ¶0048), wherein each contact via structure (140, fig. 18) contacts a top surface of a respective one of the top electrode (806, fig. 8;124, fig. 16)s and contacts the inner sidewall of the respective dielectric spacer (1002, fig. 10).
Re: Claim 22, Chang disclose(s) all the limitations of claim 21 on which this claim depends. Chang further discloses: wherein each contact via structure (140, fig. 18) of the array of contact via structure (140, fig. 18)s comprises an annular horizontal surface (¶0027; fig. 1A and 1B) that is adjoined to a bottom periphery of a first sidewall of an upper portion of the contact via structure (140, fig. 18) and is adjoined to a top periphery of a second sidewall of a downward-protruding portion of the contact via structure (140, fig. 18), wherein the bottom periphery of the first sidewall is adjoined to an inner periphery of the annular horizontal surface (¶0027; fig. 1A and 1B) and the top periphery of the second sidewall is adjoined to an outer periphery of the annular horizontal surface (¶0027; fig. 1A and 1B).
Re: Claim 25, Chang disclose(s) all the limitations of claim 21 on which this claim depends. Chang further discloses: wherein the memory material stack (122, fig.9) comprises a synthetic antiferromagnet structure (126, fig. 16), a nonmagnetic tunnel barrier layer (128, fig. 16), and a free magnetization layer (130, fig. 16), and wherein each contact via structure (140, fig. 18) comprises a metallic barrier layer (134, fig. 19) in direct contact with the top surface of the respective top electrode (806, fig. 8;124, fig. 16) and a metallic fill material portion (1802, fig. 18).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Lee et al., US PG pub. 20190165257 A1”) Discloses a magnetic memory device includes a lower interlayer insulating layer on a substrate, and a plurality of magnetic tunnel junction patterns on the lower interlayer insulating layer and isolated from direct contact with each other in a direction extending parallel to a top surface of the substrate. The lower interlayer insulating layer includes an upper surface including a recessed surface and a top surface, the recessed surface at least partially defining an inner sidewall and a bottom surface of a recess region between adjacent magnetic tunnel junction patterns, such that the recessed surface at least partially defines the recess region. The inner sidewall is inclined at an acute angle with respect to the top surface of the substrate, and the bottom surface has a shape that is convex toward the top surface of the substrate, in direction extending perpendicular to the top surface of the substrate.
* (“Chern US PG pub. 20210167277 A1”) discloses a method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.
* (“Dutta et al., US PG pub. 20200350494 A1”) discloses fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.
* (“Chuang et al., US Patent 9818935 B2”) discloses an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.
* (“Li et al., US PG pub. 20190066746 A1”) discloses varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
Allowable Subject Matter
Claim(s) 2-3, 13, 20, 23 and 24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 2 (and its dependent claim(s) 3), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: depositing and patterning a via-level metallic etch mask layer over the via-level dielectric layer; performing an anisotropic etch process that transfers a pattern in the via-level metallic etch mask layer through the via-level dielectric layer, whereby the array of via cavities is formed through the via-level dielectric layer; and simultaneously removing the array of metallic etch mask portions and the via-level metallic etch mask layer by performing a wet etch process.
Re: Claim 13, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein removal of the array of metallic etch mask portions is performed employing a wet etch process.
Re: Claim 20, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: the at least one dielectric etch stop layer comprises a stack including, from bottom to top, a first dielectric etch stop layer and a second dielectric etch stop layer; the method comprises etching portions of the second dielectric etch stop layer that underlie the array of via cavities employing a wet etch process selective to a material of the first dielectric etch stop layer; and the method further comprises etching portions of the first dielectric etch stop layer underlying openings in the second dielectric etch stop layer employing an anisotropic etch process selective to a material of the array metallic etch mask portions.
Re: Claim 23, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the at least one dielectric etch stop layer comprises a stack including, from bottom to top, a first dielectric etch stop layer and a second dielectric etch stop layer, and wherein forming the array of via cavities comprises: etching the array of via cavities through the via-level dielectric layer by an anisotropic etch process selective to the second dielectric etch stop layer; extending the array of via cavities through the second dielectric etch stop layer by a wet etch process selective to a material of the first dielectric etch stop layer; and extending the array of via cavities through the first dielectric etch stop layer by an anisotropic etch process selective to a material of the array of metallic etch mask portions.
Re: Claim 24, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: depositing and patterning a via-level metallic etch mask layer over the via-level dielectric layer prior to forming the array of via cavities; and simultaneously removing the array of metallic etch mask portions and the via-level metallic etch mask layer by a wet etch process, wherein the array of metallic etch mask portions and the via- level metallic etch mask layer comprise a same conductive metallic nitride material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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