DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS’s) submitted on 4/10/2024, 5/29/2025, 2/11/2026 were filed. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 7/8/2026 is acknowledged. Claims 17-20 are withdrawn. Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13, lines 3-5 reciting “in the source and the drain, a first one… , a second one…”; “a first one” and “a second one” are indefinite as it is unclear what “a first one” and “a second one” is referencingDue to the indefiniteness nature of the claim, the claim cannot be examined at this time.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 16 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sharma (US 20200388685 A1)
Regarding claim 1, Sharma discloses (Fig. 8) A semiconductor structure, comprising: a first gate (top 220 or bottom 220); a channel structure (210) comprising a threshold switching material (¶ [0057]), wherein the channel structure includes a layered channel (layered channel), a columnar channel, or a plurality of nanosheet channels; a first gate insulating layer (top 315 or bottom 315) disposed between the first gate and the channel structure;
a source (250) being in direct contact with the channel structure; and a drain (250) being in direct contact with the channel structure.
Regarding claim 2, Sharma discloses the semiconductor structure of claim 1, wherein the threshold switching material includes an ovonic threshold switching material, a mixed-ionic-electronic-conduction material, a phase change material (¶ [0057]), or combinations thereof.
Regarding claim 3, Sharma discloses the semiconductor structure of claim 2, wherein the threshold switching material is a chalcogenide (¶ [0057]).
Regarding claim 4, Sharma discloses the semiconductor structure of claim 2, wherein the ovonic threshold switching material comprises AsSeGe, InAsSeGe, SiAsSeGe, CAsSeGe, CTe, BTe, GeCTe, NGeCTe, or combinations thereof (BTe, ¶ [0034]).
Regarding claim 6, Sharma discloses the semiconductor structure of claim 1, wherein the source and the drain are in contact with an upper surface of the channel structure, and the first gate insulating layer (bottom 220) is disposed between the source and the drain (Fig. 8).
Regarding claim 7, Sharma discloses the semiconductor structure of claim 1, wherein the channel structure is disposed on the source and the drain, the first gate insulating layer (top 315) is disposed on the channel structure, and the first gate (top 220) is disposed on the first gate insulating layer (Fig. 8).
Regarding claim 16, Sharma discloses the semiconductor structure of claim 1. Sharma further discloses (Fig. 8) comprising an insulating layer (bottom 315), wherein the insulating layer is disposed between the source and the drain, and the channel structure is in direct contact with a plurality of sidewalls of the insulating layer, the source, and the drain.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable by Sharma (US 20200388685 A1) in view of Fraczak (US 9773978 B1) and Cheng (US 9773978 B1)
Regarding claim 5, Sharma discloses the semiconductor structure of claim 2. Sharma fails to disclose wherein the mixed-ionic-electronic-conduction material comprises CuSbGeTe, CuSbGeSTe, or a combination thereof.
Fraczak discloses mixed ionic electronic conductor used for phase change memory comprising a combination of Cu-Ge-Te (col.5, lines 23-35) and Cheng discloses new phase-change materials based on dielectric doped, Sb rich GST-225 (Ge-Sb-Te 225) can provide fast switching speed and also excellent data retention (col. 10, lines 28-30). Artisans would have appreciated Cu-Ge-Te alloys are phase change materials for high conductivity contrast and potential for low-voltage switching and GST-225 is an alloy widely used in phase-changing devices because of its reversible crystalline-amorphous phase transition. The advantage of Sb-rich GST-225 as a phase changing material would have motivated an ordinary skill in the art to mix Cu-Ge-Te with GST-225 for a multi-element alloy that may combine the high conductivity of Cu-Ge-Te with the phase-change characteristics of GST. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the phase-change materials disclosed by Franczak and Cheng to come up with a multi-layer alloy producing high conductivity and high data retention. The mixed ionic-electronic conductor material can be an alternative for the chalcogenide materials for the channel body of Sharma because they perform the same switching function.
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable by Sharma (US 20200388685 A1) in view of Shi (US 20170162710 A1)
Regarding claim 8, Sharma discloses the semiconductor structure of claim 7. Sharma discloses further comprising: a second gate (Sharma: bottom 220, Fig. 8) and a second gate insulating layer (Sharma: bottom 315, Fig. 8). wherein the second gate insulating layer is disposed on the second gate. Sharma is silent regarding the source and the drain are disposed on the second gate insulating layer.
Shi, in the same field of endeavor, discloses (Fig. 11) a double-gate transistor wherein the source and drain (705, 706, respectively) are disposed on the bottom gate insulating layer (703). Artisan in the art would have appreciated providing the gate insulating layer between the channel and the gate would physically and electrically separate the conductive gate from the semiconductive channel, preventing direct current between the gate and the channel. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the double gate transistor structure of Shi for the structure of Sharma to enhance electrical and physical separation between the channel and the bottom gate.
Regarding claim 9, Sharma discloses the semiconductor structure of claim 1. Sharma is silent regarding wherein the source and the drain are disposed on the channel structure, the first gate insulating layer is disposed on the source and the drain, and the first gate is disposed on the first gate insulating layer.
Shi discloses (Fig. 11) a double-gate transistor wherein a source and a drain (705, 706, respectively) are disposed on a channel structure (704), a first gate insulating layer (703’) is disposed on the source and the drain, and a first gate (702’) is disposed on the first gate insulating layer.
Sharma discloses a double gate transistor wherein a first gate insulating layer is between a first gate and a channel but is silent regarding a second gate insulating layer is between the channel and a second gate. Shi discloses a channel is separated from a first gate and a second gate by both a first gate insulating layer and a second gate insulating layer, respectively. As such one of ordinary skill in the art before the effective filing date of the invention would have substituted the double gate transistor of Shi for the double gate transistor of Sharma for better current leakage prevention and optimal operation.
Regarding claim 10, Sharma in view of Shi discloses the semiconductor structure of claim 9. Shi further discloses comprising (Shi: Fig. 11): a second gate (702) and a second gate insulating layer (703), wherein the second gate insulating layer is disposed on the second gate, and the channel structure is disposed on the second gate insulating layer.
Regarding claim 11. Sharma discloses the semiconductor structure of claim 1, wherein the first gate insulating layer (bottom 315) is disposed on the first gate (bottom 220). Sharma is silent regarding the source and the drain are disposed on the first gate insulating layer, and the channel structure is disposed on the source and the drain.
Shi discloses a double-gate transistor wherein (Fig. 10) a gate insulating layer (603) disposed on a gate (602) and a S/D (605, 606, respectively) disposed on the gate insulating and a channel (604) disposed on the S/D.
Artisans in the art would have appreciated a gate insulating layer between gate and S/D as well between a gate and channel would ensure current leakage prevention between conductive materials. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the transistor structure of Shi for the transistor structure of Sharma for better separation between conductive elements and optimal operations.
Regarding claim 12, Sharma discloses the semiconductor structure of claim 1, wherein the first gate insulating layer (bottom 315) is disposed on the first gate (bottom 220), the channel structure (110) is disposed on the first gate insulating layer, but is silent regarding the source and the drain are disposed on the channel structure.
Shi discloses (Fig. 11) a S/D (705, 706, respectively) disposed on a channel (704).
Artisans in the art would have appreciated the arrangement of a S/D in a double-gate transistor can be on top of the channel or on the bottom of the channel as a choice of design. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have substituted the teaching of Shi for the transistor design of Sharma to optimize device applications.
Shi discloses in Fig. 10, both S/D disposed on the lower surface of the channel, and in Fig. 11, upper surface of the channel. As such where the general conditions (S/D on upper or lower surface of the channel) of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges (one of S/D on upper surface and one of S/D on lower surface of the channel) by routine experimentation. MPEP 2144.05
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to dispose an S/D on the upper surface of the channel and the other S/D on the lower surface of the channel from a finite number of experimentations. Separating source and drain under different gates helps decouple the control of the channel from the output noted, improving stability and bandwidth.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being unpatentable by Sharma (US 20200388685 A1)
Regarding claim 14, Sharma discloses the semiconductor structure of claim 1. Sharma, in another embodiment, discloses (Fig. 16B) wherein the first gate (220) covers a plurality of sidewalls and a top surface of the channel structure.
Regarding claim 15, Sharma discloses the semiconductor structure of claim 1. Sharma, in another embodiment, discloses (Fig. 14) wherein the channel structure comprises the nanosheet channels, and the first gate surrounds the nanosheet channels.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chung (US 20220165871 A1) discloses a double-gate transistor with channel gate between the top and bottom gate/gate insulating structures; Choi (US 20140254256 A1) discloses a phase change material used as a channel for a vertical semiconductor device.
Conclusion
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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