DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I (claims 1-9 and 19-20) in the reply filed on 07/13/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Boo et al. (US PGpub: 2023/0069476 A1), herein after Boo, in view of Best et al. (US PGpub: 2022/0139446 A1), herein after Best.
Regarding claim 1, Boo teaches an apparatus, comprising:
a silicon wafer that includes a plurality of control dies (Die stack 110 have control dies and memory dies, die stack 110 can be a memory die, a logic die, a controller die, or any other kind of die as in Paragraph [0026]. 110a, 110C… can be considered control die), each control die having first bond pads (Bond pad is from where wire bonds are connected, bond pads are shown in FIG. 1A. for example through one or more wire bonds with a bond pad carried by the second tier as in Paragraph [0017]) on a first surface of the control die (110a can be considered control die which is connected to first surface of the die using wire bond 142 in FIG. 1A); and
a plurality of memory dies (110b, 110d etc. can be considered memory die), each memory die having second bond pads (144 and so on) on a second surface of the memory die, the second surface of each memory die facing the first surface of the control die (110b bottom surface is second surface which is facing first surface which is top surface of 110a) and the second bond pads (144 connected to 142 via 132. Also, upper bond pad could be 125’s and lower bond pads could be 123’s as in FIG. 2.) of each memory die bonded to corresponding first bond pads on the first surface of the memory control circuit.
Boo does not explicitly teach control die and memory dies separately.
However, difference could be easily derived by a person skilled in the art from the feature in Best wherein a control die can point to WL and control die can point to BL or vice versa) and they are on different rows/columns as shown in FIG. 5B. By this arrangement, the bit lines of the storage array 161 may be split into two half-length bit line segments 163A and 163B that each extend from an outermost row of the storage array 161 to the centrally located )
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Boo’s apparatus with teachings from Best thereby reducing the time required to retrieve data from storage cells 164 in the outermost rows (the worst case and therefore limiting retrieval time) and also reducing power required to pre-charge the bit lines.
Regarding claim 2, Boo teach the apparatus of claim 1, wherein the first surface of the control die includes a plurality of slots, each slot including a plurality of first bond pads connected, each slot occupying an area on the first surface that is equal to or greater than the area of the second surface of the memory die (FIG. 5 where each of the bond pads on the second tier is electrically connected to a corresponding individual bond pad on the first tier. In another example, in some embodiments, each bond pad in the first tier is electrically connected to two bond pads in the second tier. ….. lower bond pads 123 allow at least a portion of the lower bond pads 123 to be electrically coupled to one or more sub-stacks in the die stack 110 independently from the connection between the upper bond pads 125 and one or more other sub-stacks in the die stack 110. For example, a first lower bond pad 123a is electrically coupled to an upper bond pad 125 that is, in turn, connected to the sixth and eighth sub-stacks 110f, 110h; while a second lower bond pad 123b is electrically coupled to the fourth sub-stack 110d. Accordingly, the sixth and eighth sub-stacks 110f, 110h can be electrically coupled to the package substrate 102 through the first lower bond pad 123a, while the fourth sub-stack 110d is electrically coupled to the package substrate 102 through the second lower bond pad 123b. FIG. 2-3 and 5 and their description)
Regarding claim 3, Boo teaches the apparatus of claim 2, wherein each slot includes first bond pads connected to word line driver circuits and bit line driver circuits of the control die (FIG. 5.
Regarding claim 4, Boo teaches the apparatus of claim 2, wherein one or more of the plurality of slots is not occupied by a memory die (there are plenty of slot not occupied by memory die as in FIG. 2 and FIG. 5. Memory dies are not part of control dies anyway).
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Regarding claim 5, Boo teaches the apparatus of claim 1, wherein the plurality of memory dies includes a first memory die of a first type and a second memory die of a second type that is different to the first type (FIG. 2 and 5, memory die types can be dissimilar in nature. … For example, as illustrated, the lower tier 122 can be electrically coupled to the package substrate 102, the third and fifth sub-stacks 110c, 110e can be electrically coupled to the intermediate tiers 126, and the seventh sub-stack 110g can be electrically coupled to the upper tier 124. Similar to the benefits discussed above, the second interconnect module 520b can reduce the length of the second wire bonds 144. For example, the second wire bonds 144 electrically coupling the third sub-stack 110c to the intermediate tiers 126 can be significantly shorter than a wire bond directly to the package substrate 102.).
Regarding claim 6, Boo teaches the apparatus of claim 5, wherein the first memory die has a first number of layers of word lines and the second number of layers of word lines that is greater than the first number.
This is known to people skilled in the art where each memory die can have different number of layers of word lines or bit lines). The dies can be made different having different number of layers as known to people skilled in the art as stated in US PGpub: 2022/0066962, Ning et al. see FIG. 6 and description.
Regarding claim 7, Boo teaches the apparatus of claim 5, wherein the first memory die has nonvolatile memory cells configured to store a first number of bits per cell, the second memory die has nonvolatile memory cells configured to store a second number of bits per cell and the second number is greater than the first number.
This is known to people skilled in the art where each memory die can have different number of layers of word lines or bit lines). The dies can be made different having different number of layers as known to people skilled in the art as stated in US PGpub: 2022/0066962, Ning et al. see FIG. 6 and description.
Regarding claim 8, Boo teaches the apparatus of claim 1, wherein the plurality of memory dies are formed in a second silicon wafer, the second silicon wafer including scribe areas separating the plurality of memory dies; and probe pads located in the scribe areas, the probe pads electrically connected to components of memory arrays formed in the plurality of memory dies.
This is known to people skilled in the art where each memory die can have different number of layers of word lines or bit lines). The dies can be made different having different number of layers as known to people skilled in the art as stated in US PGpub: 2022/0066962, Ning et al. see FIG. 6 and description. row address port 212 and the column address port 222 are not shared, and therefore, during the period that the column address port 222 receives the read command R10, the row address port 212 may receive the activation command A12. In this way, the activation commands can be received without the need of waiting all the read command signals to be completely received, thus a data bus may be filled, that is, the data port 203 may transmit the data continuously, thereby avoiding the idle problem of the data bus in a certain period of time, and increasing the storage speed of the memory advantageously.
Regarding claim 9, Boo teaches the apparatus of claim 1, wherein each of the plurality of memory dies includes a 3D NAND memory array that includes a plurality of word line layers.
This is known to people skilled in the art where each memory die can have different dies different storage device (e.g., a secure digital (SD) card or a MultiMediaCard (MMC)) and the memory dies 108 are NAND memory dies as stated in US PGpub: 2023/0133965 A1, Athavale et al.
Regarding claim 19, Boo teaches a memory system comprising:
a control die that includes word line drivers connected to word line bond pads and bit line drivers connected to bit line bond pads on a first surface of the control die (Die stack 110 have control dies and memory dies, die stack 110 can be a memory die, a logic die, a controller die, or any other kind of die as in Paragraph [0026]. 110a, 110C… can be considered control die), the word line bond pads and bit line bond pads arranged in a plurality of slots, each slot sized to accommodate a corresponding memory die and each slot having word line bond pads and bit line bond pads (Bond pad is from where wire bonds are connected, bond pads are shown in FIG. 1A. for example through one or more wire bonds with a bond pad carried by the second tier as in Paragraph [0017]) on a first surface of the control die (110a can be considered control die which is connected to first surface of the die using wire bond 142 in FIG. 1A);
a plurality of memory dies (110b, 110d etc. can be considered memory die) bonded to the control die including at least a first memory die located at a first slot (110b bottom surface is second surface which is facing first surface which is top surface of 110a) and a second memory die located at a second slot, word lines of the first and second memory dies connected to word line bond pads and bit lines of the first and second memory dies connected to bit line bond pads of respective first and second slots (144 connected to 142 via 132. Also, upper bond pad could be 125’s and lower bond pads could be 123’s as in FIG. 2.); and
at least one empty slot that has word line bond pads and bit line bond pads that are not bonded (as can be seen in FIG. 5 where some of the bond pads are not connected).
Boo does not explicitly teach control die and memory dies separately.
However, difference could be easily derived by a person skilled in the art from the feature in Best wherein a control die can point to WL and control die can point to BL or vice versa) and they are on different rows/columns as shown in FIG. 5B. By this arrangement, the bit lines of the storage array 161 may be split into two half-length bit line segments 163A and 163B that each extend from an outermost row of the storage array 161 to the centrally located )
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Boo’s apparatus with teachings from Best thereby reducing the time required to retrieve data from storage cells 164 in the outermost rows (the worst case and therefore limiting retrieval time) and also reducing power required to pre-charge the bit lines.
Regarding claim 20, Boo does not explicitly teach the memory system of claim 19, wherein: the first memory die and the second memory die are different in at least one of: respective numbers of word line layers, respective numbers of bits per cell and/or respective data capacities.
This is known to people skilled in the art where each memory die can have different number of layers of word lines or bit lines). The dies can be made different having different number of layers as known to people skilled in the art as stated in US PGpub: 2022/0066962, Ning et al. see FIG. 6 and description.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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