Prosecution Insights
Last updated: October 02, 2026
Application No. 18/631,184

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Apr 10, 2024
Priority
May 12, 2023 — RE 10-2023-0061955
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
884 granted / 1088 resolved
+21.3% vs TC avg
Minimal -3% lift
Without
With
+-2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 8, 2026. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3 and 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (PG Pub 2019/0115407 A1), Won et al (PG Pub 2018/0151633 A1), and Cho et al (PG Pub 2021/0202653 A1, hereafter Cho653). Regarding claim 1, Cho teaches a display device comprising: a base layer (BL, fig. 3B); a circuit layer disposed on the base layer; and a light emitting element (OLED) disposed on the circuit layer, wherein the circuit layer comprises: a first insulating layer (30 or 10) disposed on the base layer, provided with a first contact hole (fig. 3B) defined therethrough, and comprising silicon oxide (paragraphs [0047][0049][0127]); a second insulating layer (40) disposed on the first insulating layer, provided with a second contact hole (fig. 3B) defined therethrough to correspond to the first contact hole, and comprising silicon nitride (paragraph [0056]); and a connection electrode (SE1) disposed on the second insulating layer, wherein a portion of the connection electrode is disposed in the first and second contact holes (fig. 3B), wherein the connection electrode comprises a first electrode portion disposed in the first contact hole and a second electrode portion disposed in the second contact hole (fig. 3B). Cho does not teach a minimum value of a width in one direction of the first contact hole (is equal to or greater than about 0.5 micrometers and equal to or less than about 2 micrometers. In the same field of endeavor, Won teaches a minimum value of a width (W, fig. 3) in one direction of the first contact hole is equal to or greater than about 0.5 micrometers and equal to or less than about 2 micrometers (1.5 micrometers, for example, paragraph [0051]), for the benefit of achieving high resolution (paragraph [0082]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make a minimum value of a width in one direction of the first contact hole equal to or greater than about 0.5 micrometers and equal to or less than about 2 micrometers, for the benefit of achieving high resolution. Cho does not teach a portion of the second electrode portion is in contact with an upper surface of the first insulating layer. In the same field of endeavor, Cho653 teaches a portion of the second electrode portion (PXE, fig. 5) is in contact with an upper surface of the first insulating layer (163), for the benefit of efficiently depositing the conductive layer (paragraphs [0010][0186]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make a portion of the second electrode portion in contact with an upper surface of the first insulating layer for the benefit of efficiently depositing the conductive layer. Regarding claim 2, Cho653 teaches the display device of claim 1, wherein a maximum value of the width in the one direction of the first contact hole is less than a minimum value of a width in the one direction of the second contact hole (figs. 5 and 7). Regarding claim 3, Cho653 teaches the display device of claim 1, wherein the first electrode portion is in contact with a first side surface (left side of 163, fig. 7) of the first insulating layer, the second electrode portion is in contact with a second side surface (right side of 165) of the second insulating layer, and the first side surface and the second side surface are arranged in a staggered form (figs. 5 and 7). Regarding claim 10, Cho teaches the display device of claim 1, wherein the circuit layer further comprises: a first organic layer (50, fig. 3B, paragraph [0059]) disposed on the second insulating layer and provided with a first upper contact hole defined therethrough; and an upper connection electrode (CNE) disposed in the first upper contact hole and electrically connected to the connection electrode. Regarding claim 11, Cho teaches the display device of claim 10, wherein the light emitting element comprises a first electrode (AE, fig. 3B, paragraph [0062]), a light emitting layer (EML, paragraph [0066]) disposed on the first electrode, and a second electrode (CE, paragraph [0067]) disposed on the light emitting layer, the circuit layer further comprises a second organic layer (60, paragraph [0060]) disposed on the first organic layer and provided with a second upper contact hole defined therethrough, and a portion of the first electrode is disposed in the second upper contact hole and electrically connected to the upper connection electrode (fig. 3B). Regarding claim 12, Cho teaches the display device of claim 1, wherein the circuit layer further comprises a transistor (T1, fig. 3B) disposed on the base layer, the transistor comprises a semiconductor pattern (OSP1) disposed on the base layer and a gate electrode (GE1) disposed on the first insulating layer, at least a portion of an upper surface of the semiconductor pattern is exposed through the first contact hole, and the connection electrode is electrically connected to the semiconductor pattern via the first and second contact holes (fig. 3B). Regarding claim 13, Cho teaches the display device of claim 12, wherein the circuit layer further comprises a lower insulating layer (BFL, fig. 3B) disposed on the base layer, the semiconductor pattern is disposed on the lower insulating layer, and the lower insulating layer comprises silicon oxide (paragraph [0059]), silicon nitride or silicon oxynitride. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (PG Pub 2019/0115407 A1) and Cheng et al (PG Pub 2021/0066352 A1). Regarding claim 14, Cho teaches (see claim 1) a display device comprising: a base layer; a circuit layer disposed on the base layer; and a light emitting element disposed on the circuit layer, wherein the circuit layer comprises: a first insulating layer disposed on the base layer, provided with a first contact hole defined therethrough, and comprising silicon oxide (30, paragraphs [0049][0127]); a second insulating layer (40) disposed on the first insulating layer, provided with a second contact hole defined therethrough to correspond to the first contact hole, and comprising silicon nitride (paragraph [0056]); and a connection electrode disposed on the second insulating layer, wherein the first contact hole comprises a lower portion adjacent (near) to the base layer and having a first-first slope and an upper portion adjacent (near) to the second insulating layer and having a first-second slope, Cho does not teach the first-first slope is in an angle equal to or greater than about 85 degrees and equal to or less than about 95 degrees with respect to an upper surface of the first insulating layer, and the first-second slope is in an angle equal to or greater than about 60 degrees and equal to or less than about 80 degrees with respect to the upper surface of the first insulating layer. In Applicant’s specification, the word about is defined to mean within 5% to as large as 30% of standard deviation of a value (paragraph [0048] of PG Pub). Thus, “about 85 degrees” may mean 85 minus 30 percent of 85, which is 59.5. Cheng teaches the first-first slope (α2, fig. 4) is in an angle equal to or greater than about 85 degrees and equal to or less than about 95 degrees (α2 is 75 degrees, for example, paragraph [0107]) with respect to an upper surface of the first insulating layer, and the first-second slope (α1 is less than α2, when H1 is greater than H2, and is between 50 and 75 degrees, paragraphs [0083][0107]) in an angle equal to or greater than about 60 degrees and equal to or less than about 80 degrees (50 degrees for example) with respect to the upper surface of the first insulating layer, for the benefit of preventing shorting adjacent contacts (paragraph [0084]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the first-first slope in an angle equal to or greater than about 85 degrees and equal to or less than about 95 degrees with respect to an upper surface of the first insulating layer, and the first-second slope in an angle equal to or greater than about 60 degrees and equal to or less than about 80 degrees with respect to the upper surface of the first insulating layer, for the benefit of preventing shorting adjacent contacts. Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (PG Pub 2019/0115407 A1), Won et al (PG Pub 2018/0151633 A1), and Cho et al (PG Pub 2021/0202653 A1, hereafter Cho653) as applied to claim 1 above, and further in view of Cheng et al (PG Pub 2021/0066352 A1). Regarding claim 4, the previous combination remains as applied in claim 1. Cho further teaches the display device of claim 1, wherein the first contact hole comprises a lower portion adjacent to the base layer and having a first-first slope and an upper portion adjacent to the second insulating layer and having a first- second slope (fig. 3B). Cho does not teach the first-first slope is greater than the first-second slope. In the same field of endeavor, Cheng teaches the first-first slope (α2, fig. 4) is greater than the first-second slope (α1, when H1 is greater than H2, paragraph [0083]), for the benefit of preventing shorting adjacent contacts (paragraph [0084]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the first-first slope greater than the first-second slope, for the benefit of preventing shorting adjacent contacts. Regarding claim 4, Cheng teaches the display device of claim 4, wherein the first-first slope (α2, fig. 4) is in an angle equal to or greater than about 85 degrees and equal to or less than about 95 degrees (α2 is 75 degrees, for example, paragraph [0107]) with respect to an upper surface of the first insulating layer, and the first-second slope (α1 is less than α2, when H1 is greater than H2, and is between 50 and 75 degrees, paragraphs [0083][0107]) in an angle equal to or greater than about 60 degrees and equal to or less than about 80 degrees (50 degrees for example) with respect to the upper surface of the first insulating layer, for the benefit of preventing shorting adjacent contacts (paragraph [0084]). Regarding claim 6, Cheng teaches (fig. 4) the display device of claim 4, wherein a first-first width in the one direction of the lower portion is less than a first-second width in the one direction of the upper portion. Regarding claim 7, Won teaches the display device of claim 6, wherein the first-first width in the one direction of the lower portion is equal to or greater than about 1 micrometer and equal to or less than about 1.8 micrometers (1.5 micrometers, paragraph [0051]). Allowable Subject Matter Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach “a width in the one direction of the second contact hole is uniform in a thickness direction” (claim 8) and “a portion of the second electrode portion is in contact with an upper surface of the first insulating layer” (claim 1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 10, 2024
Application Filed
Nov 26, 2024
Response after Non-Final Action
Sep 16, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
79%
With Interview (-2.7%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1088 resolved cases by this examiner. Grant probability derived from career allowance rate.

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