DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6, 8-13, 16, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over by Yoo et al. [US PGPUB 20210118824] in view of Moon et al. [US PGPUB 20210225423] in view of Pilla [US PPGUB 20090032969] (hereinafter Yoo and Moon).
Regarding claim 1, Yoo teaches a semiconductor package, comprising:
a package substrate (110/140/150, Para 22, Fig. 1) having an upper surface (112, Para 23) and a lower surface (114, Para 23) opposite to each other (Fig. 1), the package substrate including a first side portion (left sidewall, Fig. 1) and a second side portion (right sidewall, Fig. 1) extending in a direction parallel to a first direction and facing each other (Fig. 1);
a first group of semiconductor chips (300a-e, Para 32, Fig. 1) disposed on the upper surface of the package substrate (Fig. 1), the first group of semiconductor chips including a first lower semiconductor chip (300a, Fig. 1) and a second lower semiconductor chip (300e, Fig. 1) stacked on the first lower semiconductor chip (Fig. 1) and respectively comprise first surfaces facing upwards on which chip pads (310, Para 36, Fig. 1/2) are formed, and the first group of semiconductor chips are sequentially offset in a second direction perpendicular to the first direction (Fig. 1);
a second group of semiconductor chips (300f-j, Para 32, Fig. 1) disposed on the first group of semiconductor chips (Fig. 1), the second group of semiconductor chips including a first upper semiconductor chip (300f, Fig. 1) and a second upper semiconductor chip (300j, Fig. 1) stacked on the first upper semiconductor chip (Fig. 1) and respectively comprise a first surfaces facing upwards on which upper chip pads (310, Para 36, Fig. 1/2) are formed, and the second group of semiconductor chips are sequentially offset in the direction opposite to the second direction (Fig. 1);
a plurality of first bonding wires (330, Para 36) electrically connecting the chip pads to a plurality of first substrate pads (120, Para 36) of the package substrate (Fig. 1);
a plurality of second bonding wires (330, Para 36) electrically connecting the upper chip pads to a plurality of second substrate pads (120, Para 36) of the package substrate (Fig. 1); and
a molding member (500, Para 68) covering the first group of semiconductor chips and the second group of semiconductor chips on the upper surface of the package substrate (Fig. 1),
wherein;
a first lower adhesive film (320a, Para 53) is stacked directly on the upper surface of the package substrate (Fig. 1),
the first lower semiconductor chip (300a, Para 53) is stacked directly on an upper surface of the first lower adhesive film (Fig. 1),
a second lower adhesive film (320b, Para 62) is stacked directly on an upper surface of the first lower semiconductor chip (Fig. 1), and
the second upper semiconductor chip overlaps an overhang region of the first lower semiconductor chip that protrudes from a side of the second lower semiconductor chip (Fig. 1).
Yoo does not specifically disclose wherein:
the second lower semiconductor chip is stacked directly on an upper surface of the second lower adhesive film,
a first upper adhesive film is stacked directly on an upper surface of the second lower semiconductor chip,
the first upper semiconductor chip is stacked directly on an upper surface of the first upper adhesive film,
a second upper adhesive film is stacked directly on an upper surface of the first upper semiconductor chip, and
the second upper semiconductor chip is stacked directly on an upper surface of the second upper adhesive film.
Moreover, it is noted that Yoo discloses that the number, sizes, locations, etc., of the second semiconductor devices 300 are exemplarily illustrated, and it is understood that one or more other exemplary embodiments are not limited thereto (Para 37).
Referring to the invention of Moon, Moon discloses a memory stack, wherein the number of die in the stack can be increased or decreased (Para 42).
In view of such teaching by Moon, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the have the number of chips in the invention of Yoon increased or decreased for the intended purpose, wherein decreased number of chips could result in a more compact package or reduce heat generation in the package.
Referring to the invention of Pilla, Pilla teaches various packages comprising varying chip quantity and different offsetting structure, wherein in an instance (Fig. 2), the package comprises a first lower chip 104, a second lower chip 112 on the first lower chip, a first upper chip 104’ on the second lower chip, and a second upper chip 112’ on the first upper chip, wherein
the first lower chip 104 and the second lower chip 112 are sequentially offset to form a first group 102,
the first upper chip 104’ and the second upper chip 112’ are sequentially offset to form a first group 102’, and
wherein the second upper semiconductor chip overlaps an overhang region of the first lower semiconductor chip that protrudes from a side of the second lower semiconductor chip.
In view of such teaching by Pilla (various packaging structures), it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to modify the invention of Yoo to employ a reduced number of stacked chips as taught by Pilla’s 4 chips configuration, wherein such modification would reduce package size.
Moreover, Pilla’s invention (Fig. 2) and Yoo’s disclosure are within the same field of semiconductor packaging, thus, a person having ordinary skills in the art will find it obvious to try (MPEP 2143.I.E) Pilla’s configuration along with Yoo’s disclosure at least based on the rationale of relying on known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art (MPEP 2143.I.F).
Regarding claim 2, the modified invention of Yoo teaches a semiconductor package wherein the first substrate pads are arranged along the first side portion of the package substrate (Yoo, Fig. 1/2), and the second substrate pads are arranged along the second side portion of the package substrate (Yoo, Fig. 1/2).
Regarding claim 4, the modified invention of Yoo teaches a semiconductor package wherein the first lower adhesive film, the second lower adhesive film, the first upper adhesive film, and the second upper adhesive film are each a die attach film (Yoo, Para 59).
Regarding claim 6, the modified invention of Yoo teaches a semiconductor package wherein a first side surface of the first lower semiconductor chip and a first side surface of the second lower semiconductor chip that are adjacent to the first side portion of the package substrate are spaced apart from each other by a first distance (Yoo, Fig. 1), and
wherein a second side surface of the first upper semiconductor chip and a second side surface of the second upper semiconductor chip that are adjacent to the second side portion of the package substrate are spaced apart from each other by the first distance (Yoo, Fig. 1).
Regarding claim 8, the modified invention of Yoo teaches a semiconductor package wherein a first side surface of the first lower semiconductor chip and a first side surface of the second upper semiconductor chip that are adjacent to the first side portion of the package substrate are located on a first plane (Yoo, Fig. 1), and
wherein a second side surface of the second lower semiconductor chip and a second side surface of the first upper semiconductor chip that are adjacent to the second side portion of the package substrate are located on a second plane (Yoo, Fig. 1).
Regarding claim 9, the modified invention of Yoo teaches a semiconductor package wherein the plurality of first bonding wires include a first lower wire that connects the chip pad of the first lower semiconductor chip to the first substrate pad and a second lower wire that electrically connects the chip pad of the second lower semiconductor chip to the chip pad of the first lower semiconductor chip (Yoo, Fig. 1), and
wherein the plurality of second bonding wires include a first upper wire that connects the chip pad of the first upper semiconductor chip to the second substrate pad and a second upper wire that connects the chip pad of the second upper semiconductor chip to the first upper semiconductor chip (Yoo, Fig. 1).
Regarding claim 10, the modified invention of Yoo teaches a semiconductor package further comprising:
external connection members (600, Yoo, Para 69) disposed on external connection pads (130, Yoo, Para 69) on the lower surface of the package substrate (Yoo, Fig. 1).
Regarding claim 11, Yoo teaches a semiconductor package comprising:
a package substrate (110, Para 22);
a first group of semiconductor chips (300a-e, Para 32, Fig. 1) disposed on the package substrate (Fig. 1), the first group of semiconductor chips including a first lower semiconductor chip (300a, Fig. 1) and a second lower semiconductor chip (300e, Fig. 1) that are stacked offset in a first horizontal direction (Fig. 1) such that a first surface of each of the first and second lower semiconductor chips on which chip pads (310, Para 36, Fig. 1/2) are formed face upward (Fig. 1/2);
a second group of semiconductor chips (300f-j, Para 32, Fig. 1) disposed on the first group of semiconductor chips (Fig .1), the second group of semiconductor chips including a first upper semiconductor chip (300f, Fig. 1) and a second upper semiconductor chip (300j, Fig. 1) that are stacked offset in a direction opposite to the first horizontal direction (Fig. 1) such that a first side of each of the first and second upper semiconductor chips on which upper chip pads (310, Para 36, Fig. 1/2) are formed face upward (Fig. 1);
a plurality of first bonding wires (330, Para 36) electrically connecting the chip pads to a plurality of first substrate pads (120, Para 36) of the package substrate (Fig. 1/2);
a plurality of second bonding wires (330, Para 36) electrically connecting the upper chip pads to a plurality of second substrate pads (120, Para 36) of the package substrate (Fig. 1/2); and
a molding member (500, Para 68) covering the first group of semiconductor chips and the second group of semiconductor chips on the package substrate (Fig. 1),
wherein each of the first group of semiconductor chips and the second group of semiconductor chips has a first side surface and a second side surface opposite to the first side surface (Fig. 1),
wherein the first side surfaces of the first group of semiconductor chips are arranged in one-to-one correspondence with the first side surfaces of the second group of semiconductor chips (Fig. 1); and
wherein;
a first lower adhesive film (320a, Para 53) is stacked directly on the upper surface of the package substrate (Fig. 1),
the first lower semiconductor chip (300a, Para 53) is stacked directly on an upper surface of the first lower adhesive film (Fig. 1),
a second lower adhesive film (320b, Para 62) is stacked directly on an upper surface of the first lower semiconductor chip (Fig. 1), and
the second upper semiconductor chip overlaps an overhang region of the first lower semiconductor chip that protrudes from a side of the second lower semiconductor chip (Fig. 1).
Yoo does not specifically disclose wherein:
the second lower semiconductor chip is stacked directly on an upper surface of the second lower adhesive film,
a first upper adhesive film is stacked directly on an upper surface of the second lower semiconductor chip,
the first upper semiconductor chip is stacked directly on an upper surface of the first upper adhesive film,
a second upper adhesive film is stacked directly on an upper surface of the first upper semiconductor chip, and
the second upper semiconductor chip is stacked directly on an upper surface of the second upper adhesive film.
Moreover, it is noted that Yoo discloses that the number, sizes, locations, etc., of the second semiconductor devices 300 are exemplarily illustrated, and it is understood that one or more other exemplary embodiments are not limited thereto (Para 37).
Referring to the invention of Moon, Moon discloses a memory stack, wherein the number of die in the stack can be increased or decreased (Para 42).
In view of such teaching by Moon, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the have the number of chips in the invention of Yoon increased or decreased for the intended purpose, wherein decreased number of chips could result in a more compact package or reduce heat generation in the package.
Referring to the invention of Pilla, Pilla teaches various packages comprising varying chip quantity and different offsetting structure, wherein in an instance (Fig. 2), the package comprises a first lower chip 104, a second lower chip 112 on the first lower chip, a first upper chip 104’ on the second lower chip, and a second upper chip 112’ on the first upper chip, wherein
the first lower chip 104 and the second lower chip 112 are sequentially offset to form a first group 102,
the first upper chip 104’ and the second upper chip 112’ are sequentially offset to form a first group 102’, and
wherein the second upper semiconductor chip overlaps an overhang region of the first lower semiconductor chip that protrudes from a side of the second lower semiconductor chip.
In view of such teaching by Pilla (various packaging structures), it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to modify the invention of Yoo to employ a reduced number of stacked chips as taught by Pilla’s 4 chips configuration, wherein such modification would reduce package size.
Moreover, Pilla’s invention (Fig. 2) and Yoo’s disclosure are within the same field of semiconductor packaging, thus, a person having ordinary skills in the art will find it obvious to try (MPEP 2143.I.E) Pilla’s configuration along with Yoo’s disclosure at least based on the rationale of relying on known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art (MPEP 2143.I.F).
Regarding claim 12, the modified invention of Yoo specifically in view of Pilal teaches a semiconductor package wherein the first side surface of the first lower semiconductor chip (104, Pilla, Fig. 2) and the first side surface of the second upper semiconductor chip (112’, Pilla, Fig. 2) are located on a first plane (Pilla, Fig. 2), and
wherein the first side surface of the second lower semiconductor chip (112, Pilla, Fig. 2) and the first side surface of the first upper semiconductor chip (104’, Pilla, Fig. 2) are located on a second plane (Pilla, Fig. 2).
Regarding claim 13, the modified invention of Yoo specifically in view of Pilal teaches a semiconductor package wherein the first side surface of first lower semiconductor chip (104, Pilla, Fig. 2) and the first side surface of the second lower semiconductor chip (112, Pilla, Fig. 2) are spaced apart by a first distance (Pilla, Fig. 2), and
wherein the first side surface of the second upper semiconductor chip (112’, Pilla, Fig. 2) and the first side surface of the first upper semiconductor chip (104’, Pilla, Fig. 2) are spaced apart by the first distance (Pilla, Fig. 2).
Regarding claim 16, the modified invention of Yoo teaches a semiconductor package wherein the first lower adhesive film, the second lower adhesive film, the first upper adhesive film, and the second upper adhesive film are each a die attach film (Yoo, Para 59).
Regarding claim 18, the modified invention of Yoo teaches a semiconductor package wherein the first substrate pads are arranged spaced apart along a first side portion of the package substrate adjacent to the first side surfaces of the first group of semiconductor chips and the second group of semiconductor chips (Yoo, Fig. 1/2), and
the second substrate pads are arranged spaced apart along a second side portion of the package substrate opposite to the first side portion (Yoo, Fig. 1/2).
Regarding claim 19, the modified invention of Yoo teaches a semiconductor package wherein the plurality of first bonding wires include a lower wire that connects the chip pads of the first and second lower semiconductor chips to each other (Yoo, Fig. 1), and
wherein the plurality of second bonding wires include an upper wire that connects the upper chip pads of the first and second upper semiconductor chips to each other (Yoo, Fig. 1).
Regarding claim 20, Yoo teaches a semiconductor package, comprising:
a package substrate (110, Para 22);
a first group of semiconductor chips (300a-e, Para 32, Fig. 1) disposed on the package substrate (Fig. 1), the first group of semiconductor chips including a first lower semiconductor chip (300a, Fig. 1) and a second lower semiconductor chip (300e, Fig. 1) that are stacked offset in a first horizontal direction (Fig. 1) such that a first surface of each of the first and second lower semiconductor chips on which chip pads (310, Para 36, Fig. 1/2) are formed face upward (Fig. 1);
a second group of semiconductor chips (300f-j, Para 32, Fig. 1) disposed on the first group of semiconductor chips (Fig. 1), the second group of semiconductor chips including a first upper semiconductor chip (300f, Fig. 1) and a second upper semiconductor chip (300j, Fig. 1) that are stacked offset in a direction opposite to the first horizontal direction (Fig. 1) such that a first surface of each of the first and second upper semiconductor chips on which upper chip pads (310, Para 36, Fig. 1/2) are formed face upward (Fig. 1);
a plurality of first bonding wires (330, Para 36) electrically connecting the chip pads to a plurality of first substrate pads (120, Para 36) of the package substrate (Fig. 1);
a plurality of second bonding wires (330, Para 36) electrically connecting the upper chip pads to a plurality of second substrate pads (120, Para 36) of the package substrate (Fig. 1); and
a molding member (500, Para 68) covering the first group of semiconductor chips and the second group of semiconductor chips on the package substrate (Fig. 1),
wherein;
a first lower adhesive film (320a, Para 53) is stacked directly on the upper surface of the package substrate (Fig. 1),
the first lower semiconductor chip (300a, Para 53) is stacked directly on an upper surface of the first lower adhesive film (Fig. 1),
a second lower adhesive film (320b, Para 62) is stacked directly on an upper surface of the first lower semiconductor chip (Fig. 1), and
the second upper semiconductor chip overlaps an overhang region of the first lower semiconductor chip that protrudes from a side of the second lower semiconductor chip (Fig. 1),
each of the first group of semiconductor chips and the second group of semiconductor chips has a first side surface adjacent to a first side portion of the package substrate and a second side surface opposite to the first side portion,
each of the first and second lower semiconductor chips overlap with corresponding ones of the first and second upper semiconductor chips (Fig. 1),
the first side surface of the first lower semiconductor chip and the first side surface of the second upper semiconductor chip are located on a first plane (Fig. 1), and
the first side surfaces of the second lower semiconductor chip and the first upper semiconductor chip are located on a second plane different than the first plane (Fig. 1).
Yoo does not specifically disclose wherein:
the second lower semiconductor chip is stacked directly on an upper surface of the second lower adhesive film,
a first upper adhesive film is stacked directly on an upper surface of the second lower semiconductor chip,
the first upper semiconductor chip is stacked directly on an upper surface of the first upper adhesive film,
a second upper adhesive film is stacked directly on an upper surface of the first upper semiconductor chip, and
the second upper semiconductor chip is stacked directly on an upper surface of the second upper adhesive film.
Moreover, it is noted that Yoo discloses that the number, sizes, locations, etc., of the second semiconductor devices 300 are exemplarily illustrated, and it is understood that one or more other exemplary embodiments are not limited thereto (Para 37).
Referring to the invention of Moon, Moon discloses a memory stack, wherein the number of die in the stack can be increased or decreased (Para 42).
In view of such teaching by Moon, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the have the number of chips in the invention of Yoon increased or decreased for the intended purpose, wherein decreased number of chips could result in a more compact package or reduce heat generation in the package.
Referring to the invention of Pilla, Pilla teaches various packages comprising varying chip quantity and different offsetting structure, wherein in an instance (Fig. 2), the package comprises a first lower chip 104, a second lower chip 112 on the first lower chip, a first upper chip 104’ on the second lower chip, and a second upper chip 112’ on the first upper chip, wherein
the first lower chip 104 and the second lower chip 112 are sequentially offset to form a first group 102,
the first upper chip 104’ and the second upper chip 112’ are sequentially offset to form a first group 102’, and
wherein the second upper semiconductor chip overlaps an overhang region of the first lower semiconductor chip that protrudes from a side of the second lower semiconductor chip.
In view of such teaching by Pilla (various packaging structures), it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to modify the invention of Yoo to employ a reduced number of stacked chips as taught by Pilla’s 4 chips configuration, wherein such modification would reduce package size.
Moreover, Pilla’s invention (Fig. 2) and Yoo’s disclosure are within the same field of semiconductor packaging, thus, a person having ordinary skills in the art will find it obvious to try (MPEP 2143.I.E) Pilla’s configuration along with Yoo’s disclosure at least based on the rationale of relying on known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art (MPEP 2143.I.F).
Regarding claim 21, the modified invention of Yoo specifically in view of Pilal teaches a semiconductor package wherein the molding member is disposed directly on an upper surface of the second upper semiconductor chip and part of the upper surface of the first lower semiconductor chip (Yoo, Fig. 1).
Regarding claim 22, the modified invention of Yoo specifically in view of Pilal teaches a semiconductor package wherein the molding member is disposed directly on an upper surface of the second upper semiconductor chip and part of the upper surface of the first lower semiconductor chip (Yoo, Fig. 1).
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Moon and Pilla and further in view of Jeong et al. [US PGPUB 20210249382] (hereinafter Jeong).
Regarding claim 5 and 17, the modified invention of Yoo teaches the limitation of claims 3 and 15 upon which they depend respectively.
The modified invention does not specifically disclose a semiconductor package wherein each of the first lower adhesive film, the second lower adhesive film, the first upper adhesive film, and the second upper adhesive film has a thickness of 10 micrometers (μm) to 40 μm.
Referring to the invention of Jeong, Jeong teaches a semiconductor package similar to that of Yoo, wherein the chips of the package are bonded together using adhesive film (420/520/620, Para 70), and wherein the thickness of the adhesive film is 20 μm (Para 27).
In view of such teaching by Jeong, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Jeong at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) –wherein adhesive film will obviously provide adequate adhesion between chips.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Moon and Pilla and further in view of Okada et al. [US PGPUB 20100187690] (hereinafter Okada).
Regarding claim 7 and 14, the modified invention of Yoo teaches the limitation of claims 3 and 15 upon which they depend respectively.
The modified invention does not specifically disclose a semiconductor package wherein the first distance is within a range of 200 micrometers (μm) to 300 μm.
Referring to the invention of Okada, Okada teaches a semiconductor package in which stacking chips, and wherein there is an offset of 280 μm with respect to side surface of the chips (Para 44, Fig. 2).
In view of such teaching by Okada, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the Yoo comprise the teachings of Okada at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) -wherein the distance would allow for effective electrical connection of the bonding wires and chips pads and/or preventing a collapse of the stack.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISMAIL A MUSE whose telephone number is (571)272-1470. The examiner can normally be reached Monday - Friday 8:00 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571)270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
Prosecution Insights