DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B in the reply filed on 7/28/2026 is acknowledged.
Claims 4, 7-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/28/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/10/2024, 8/20/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitsumoto et al (US 2022/0077044; hereinafter Mitsumoto).
Regarding claim 1, Fig 2 of Mitsumoto discloses a semiconductor device comprising:
a wiring board (20; Fig 2; ¶ [0047]) having a first surface (bottom surface; Fig 2) and a second surface (Top surface; Fig 2) opposite to the first surface and including a wiring pattern (22a/22b/23a/23b/24/21; Fig 2; ¶ [0049]) disposed on the second surface;
a semiconductor package (1; Fig 2; ¶ [0034]) including a semiconductor chip (3; Fig 2; ¶ [0035]) formed with a semiconductor element (3; Fig 2; ¶ [0035]), an insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) having a first surface (Top surface; Fig 2) on which the semiconductor chip (3; Fig 2; ¶ [0035] is arranged and a second surface (Bottom surface; Fig 2), and an element pad (12b; Fig 2; ¶ [0037]) being electrically connected to the semiconductor chip (3; Fig 2; ¶ [0035]), the semiconductor package being mounted on the wiring board (20; Fig 2; ¶ [0047]) so that the element pad (12b; Fig 2; ¶ [0037]) is connected (Fig 2) to the wiring pattern (22a/22b/23a/23b/24/21; Fig 2; ¶ [0049]); and
a heat dissipation member (13; Fig 2; ¶ [0037]) disposed opposite to the wiring board (20; Fig 2; ¶ [0047]) with respect to the semiconductor package, the heat dissipation member (13; Fig 2; ¶ [0037]) facing the second surface (Bottom surface; Fig 2) of the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) and being thermally connected (¶ [0038]) to the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]), wherein
the wiring pattern (22a/22b/23a/23b/24/21; Fig 2; ¶ [0049]) includes a heat dissipation pattern (23a1; Fig 2; ¶ [0049]) that is connected to the semiconductor element and allows a current to flow according to an operation of the semiconductor element (¶ [0077]), and
the semiconductor device (1; Fig 2; ¶ [0034]) further comprising:
a heat dissipation connection member (5b; Fig 2; ¶ [0035]) disposed between the heat dissipation pattern (23a1; Fig 2; ¶ [0049]) and the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) to thermally connect the heat dissipation pattern and the insulating heat dissipation substrate (Fig 2).
Regarding claim 2, Fig 2 of Mitsumoto discloses the semiconductor package includes a heat dissipation pad (16; Fig 2; ¶ [0065]) connected to the heat dissipation pattern (23a1; Fig 2; ¶ [0049]) and a heat dissipation via (5b; Fig 2; ¶ [0035]) as the heat dissipation connection member (5b; Fig 2; ¶ [0035]) connecting the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) and the heat dissipation pad (16; Fig 2; ¶ [0065]), and
the heat dissipation pattern (23a1; Fig 2; ¶ [0049]) is thermally connected (Fig 2) to the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) through the heat dissipation pad (16; Fig 2; ¶ [0065]) and the heat dissipation via (5b; Fig 2; ¶ [0035]).
Regarding claim 3, Fig 2 of Mitsumoto discloses the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) has a heat dissipation wiring layer (12a; Fig 2; ¶ [0037]) on the first surface (Top surface; Fig 2) thereof and at a position different (Fig 2) from a position where the semiconductor chip (3; Fig 2; ¶ [0035]) is arranged; and
the heat dissipation pattern (23a1; Fig 2; ¶ [0049]) is electrically connected to the heat dissipation wiring layer (12a; Fig 2; ¶ [0037]) through the heat dissipation pad (16; Fig 2; ¶ [0065]) and the heat dissipation via (5b; Fig 2; ¶ [0035]).
Regarding claim 9, Fig 2 of Mitsumoto discloses the insulating heat dissipation substrate (11; Fig 2; ¶ [0037]) is formed with a chip wiring layer (¶ [0037]),
the semiconductor chip (3; Fig 2; ¶ [0035]) includes a semiconductor substrate (¶ [0044]) containing gallium nitride (¶ [0044]),
the semiconductor chip (3; Fig 2; ¶ [0035]) has, as the semiconductor element (3; Fig 2; ¶ [0035]), a horizontal element that has a drain electrode (3d; Fig 2; ¶ [0045]), a source electrode (3s; Fig 2; ¶ [0045]) and a gate electrode (3g; Fig 3; ¶ [0045]), and allows a current to flow along a planar direction of the semiconductor substrate (Fig 2),
the semiconductor chip (3; Fig 2; ¶ [0035]) has a rear surface electrode (3d; Fig 2) electrically connected to the chip wiring layer (12a; Fig 2) on a surface facing the insulating heat dissipation substrate, and
the source electrode (3s; Fig 2) is connected to the rear surface electrode through the chip wiring layer. (Fig 2)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsumoto et al (US 2022/0077044; hereinafter Mitsumoto) and further in view of Sakaniwa et al (US 2023/0319975; hereinafter Sakaniwa).
Regarding claim 5, Mitsumoto does not expressly disclose a high thermal conductive member disposed between the insulating heat dissipation substrate and the heat dissipation member, the high thermal conductive member being made of a material having a thermal conductivity higher than that of the insulating heat dissipation substrate.
In the same field of endeavor, Fig 1 of Sakaniwa discloses a high thermal conductive member (13; Fig 1; ¶ [0041]) disposed between an insulating heat dissipation substrate (11; Fig 1; ¶ [0042]) and a heat dissipation member (31; Fig 1; ¶ [0042]), the high thermal conductive member (13; Fig 1; ¶ [0041]) being made of a material (¶ [0041]) having a thermal conductivity higher (¶ [0041]) than that of the insulating heat dissipation substrate (11; Fig 1; ¶ [0042]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a high thermal conductive member is disposed between the insulating heat dissipation substrate and the heat dissipation member because the thermal conductive member has an effect of improving the heat radiation characteristics by spreading heat generated in the semiconductor element mounted on the insulating resin circuit substrate (¶ [0041]).
Regarding claim 6, Mitsumoto in view of Sakaniwa as modified above in claim 5 (Fig 1 of Sakaniwa in particular) discloses the high thermal conductive member (13; Fig 1; ¶ [0041] of Sakaniwa) is thicker (Fig 1 of Sakaniwa) than the insulating heat dissipation substrate (11; Fig 1; ¶ [0042] of Sakaniwa).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mitsumoto et al (US 2022/0077044; hereinafter Mitsumoto) and further in view of Muramoto et al (US 2026/0133245; hereinafter Muramoto).
Regarding claim 10, Fig 2 of Mitsumoto discloses the semiconductor package has a sealing member (8; Fig 2; ¶ [0035]) sealing the semiconductor chip,
the element pad (12b; Fig 2; ¶ [0037]) and the semiconductor chip (3; Fig 2; ¶ [0035]) are electrically connected to each other through a through-via (5a; Fig 2) in the sealing member.
However Mitsumoto does not expressly disclose a multilayer sealing member and the multilayer sealing member includes a plurality of film members integrated to each other.
In the same field of endeavor, Fig 1 of Muramoto discloses a multi layer sealing member (8/12; Fig 1; ¶ [0022]) and the multilayer sealing member includes plurality of film members (8/12; Fig 1; ¶ [0022]) integrated to each other (Fig 1).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a sealing member is a multilayer sealing member and the multilayer sealing member includes a plurality of film members integrated to each other as taught by Muramoto in order to seal the semiconductor chip and prevent the chip from moisture.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ikeda et al (US 2025/0379116)
Kim et al (US 2024/0145329)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
