DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/10/2024 and 04/10/2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the first I T-line" and "the first PQ T-line" in lines 14 and 19, respectively. There is insufficient antecedent basis for this limitation in the claim.
It is suggested to change "the first I T-line" to --the I T-line--; and "the first PQ T-line" to --the PQ T-line--.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paramesh et al. (US 11,251,859 B2).
Regarding claim 1, Paramesh et al. (figures 4 and 5) disclose a beamforming front end (BFFE) for a receiver, the BFFE comprising: a first signal chain (bottom antenna to Digital Signal Processor) configured to receive a first signal (X1), produce a first I signal by amplifying the first signal by a first I gain value (programmable-gain amplifier and programmable phase-shifter W11), and produce a first PQ signal by amplifying the first signal by a first Q gain value (programmable-gain amplifier and programmable phase-shifter W21, it is noted that one of W11 and W21 for I signal, and the other one for Q signal), wherein the first I signal and first PQ signal are mutually in-phase and the first I gain value and first Q gain value correspond to a first phase shift; a second signal chain (middle antenna to Digital Signal Processor) configured to receive a second signal (figure 4 shows X1 signal, but it should be X2 signal), produce a second I signal by amplifying the second signal by a second I gain value (W12), and produce a second PQ signal by amplifying the second signal by a second Q gain value (W22), wherein the second I signal and second PQ signal are mutually in-phase and the second I gain value and second Q gain value correspond to a second phase shift; an I combiner circuit (bottom combiner) configured to produce a combined I signal by summing respective values of the first and second I signals (combining signals through W11 and W12 to generate Y1 signal); a PQ combiner circuit (top combiner) configured to produce a combined PQ signal by summing respective values of the first and second PQ signals (combining signals through W21 and W22 to generate Y2 signal); and a converter circuit (LO Generation and upper and lower Down-converion circuits) configured to produce, based on the combined I signal and combined PQ signal, an output signal corresponding to the first signal phase-shifted by the first phase shift and the second signal phase-shifted by the second phase shift (column 4, lines 5-18).
Regarding claim 9, Paramesh et al. disclose the BFFE of claim 1, wherein the first signal chain comprises: a first I Variable Gain Amplifier (VGA) (programmable-gain amplifier and programmable phase-shifter W11) configured to produce the first I signal by amplifying the first signal by the first I gain value, and a first Q VGA (programmable-gain amplifier and programmable phase-shifter W21) configured to produce the first PQ signal by amplifying the first signal by the first Q gain value; and wherein the second signal chain comprises: a second I VGA (programmable-gain amplifier and programmable phase-shifter W12) configured to produce the second I signal by amplifying the second signal by the second I gain value, and a second Q VGA (programmable-gain amplifier and programmable phase-shifter W22) configured to produce the second PQ signal by amplifying the second signal by the second Q gain value (see figure 4, and figure 5 also shows the amplifiers after low noise amplifiers are VGAs).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-4, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al. in view of Dehlink et al. (US 9,411,039 B2).
Regarding claim 2, Paramesh et al. disclose the BFFE of claim 1 above. In addition Paramesh et al. disclose wherein the converter circuit comprises: a quadrature local oscillator circuit configured to generate an in-phase (I) local oscillator signal (signal from LO Generation to upper Down-conversion) and a quadrature (Q) local oscillator signal (signal from LO Generation to lower Down-conversion); an I mixer (upper Down-conversion) configured to produce a converted I signal by mixing the I local oscillator signal with the combined I signal; a Q mixer (lower Down-conversion) configured to produce a converted Q signal by mixing the Q local oscillator signal with the combined PQ signal (see figure 4). Paramesh et al. do not explicitly disclose the Q local oscillator signal having a phase different than the I local oscillator signal; and a combiner circuit configured to produce the output signal by combining the converted I signal and the converted Q signal. However, Dehlink et al. (figure 6) disclose a quadrature local oscillator circuit (LO 616, quadrature generator 618, in-phase mixer 614, and quadrature mixer 620) generates an in-phase (I) local oscillator signal and a quadrature (Q) local oscillator signal, the Q local oscillator signal having a phase different than the I local oscillator signal (column 3, line 61 – column 4, line 14); and a combiner circuit (612 combining in-phase and quadrature signals) configured to produce the output signal by combining the converted I signal and the converted Q signal (column 4, lines 15-36). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the teaching of the Q local oscillator signal having a phase different than the I local oscillator signal and the combiner circuit of Dehlink et al. to the quadrature local oscillator circuit of Paramesh et al. for converting I and Q signals and combining them to provide a channel output.
Regarding claim 3, Paramesh et al. and Dehlink et al disclose the BFFE of claim 2. In addition, Dehlink et al. disclose wherein the Q local oscillator signal is 90° out of phase with the I local oscillator signal (column 4, lines 46-56). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the teaching of the Q local oscillator signal is 90° out of phase with the I local oscillator signal of Dehlink et al. to the quadrature local oscillator circuit of Paramesh et al. as a system design preference for serving the same function as providing I and Q local oscillator signals for converting I and Q signals.
Regarding claim 4, Paramesh et al. and Dehlink et al disclose the BFFE of claim 3 above. In addition, Paramesh disclose wherein the quadrature local oscillator circuit comprise: a local oscillator (figure 4, LO Generation) producing a local oscillator signal. And Dehlink et al. disclose wherein the quadrature local oscillator circuit comprise: a local oscillator (figure 6, LO 616) producing a local oscillator signal; and a quadrature generator (618) producing the Q local oscillator signal from the local oscillator signal (signal to quadrature mixing circuit 620) (column 3, line 61 – column 4, line 14). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the quadrature generator of Dehlink et al. to the quadrature local oscillator circuit of Paramesh et al. as a system design preference for serving the same function as providing Q local oscillator signal for converting Q signal.
Regarding claim 15, Paramesh et al. (figures 4 and 5) disclose a method of performing beamforming in a receiver, the method comprising: producing a plurality of I signals (signals going to W11, W12 … W1N) and a plurality of PQ signals (signals going to W21, W22 … W2N) based on a plurality of received signals (X1 – XN) and a plurality of gain value pairs (programmable-gain amplifier and programmable phase-shifters W11-W21, W12-W22 … W1N-W2N) by, for each received signal and the corresponding gain value pair: producing the corresponding I signal by amplifying that received signal by an I gain value of that gain value pair (signals going through W11, W12 … W1N), and producing the corresponding PQ signal by amplifying that received signal by a Q gain value of that gain value pair (signals going through W21, W22 … W2N); producing, using the plurality of I signals, a combined I signal having a value corresponding to a sum of values of the plurality of I signals (Y1 from bottom combiner); producing, using the plurality of PQ signals, a combined PQ signal having a value corresponding to a sum of values of the plurality of PQ signals (Y2 from top combiner), wherein the corresponding I signal for each received signal has the same phase as the corresponding PQ signal for that received signal, respectively phase shifted by an amount corresponding to the corresponding gain value pair of the plurality of gain value pairs (column 4, lines 5-18). Paramesh et al. do not explicitly disclose producing, using the combined I signal and the combined PQ signal, an output signal corresponding to a sum of the plurality of received signals. However, Dehlink et al. disclose a method of performing beamforming in a receiver comprising producing an output signal by combining I signal and Q signal (column 3, line 61 – column 4, line 14). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the producing an output signal by combining I signal and Q signal of Dehlink et al. to the method of Paramesh et al. for producing channel output signal from the combined I signal and the combined PQ signal.
Regarding claim 16, Paramesh et al. and Dehlink et al disclose the method of claim 15 above. In addition, Paramesh et al. (figure 4) disclose producing an in-phase local oscillator signal and a quadrature local oscillator signal (LO Generation to upper and lower Down-converion circuits); producing a converted I signal by mixing the in-phase local oscillator signal with the combined I signal (using lower Down-converion circuit); producing a converted Q signal by mixing the quadrature local oscillator signal with the combined PQ signal (using upper Down-converion circuit). And Dehlink et al. disclose producing the output signal by combining the converted I and Q signals (column 3, line 61 – column 4, line 14). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the producing an output signal by combining the converted I and Q signals of Dehlink et al. to the method of Paramesh et al. for producing channel output signal.
Claim(s) 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al. in view of Dehlink et al. and further in view of Chakraborty (US 9,960,883 B1).
Regarding claim 5, Paramesh et al. and Dehlink et al disclose the BFFE of claim 4 above. Paramesh et al. and Dehlink et al do not explicitly disclose wherein the quadrature generator comprises a hybrid quadrature generator. However, Chakraborty discloses a quadrature generator comprises a hybrid quadrature generator (column 11, lines 26-43). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the hybrid quadrature generator of Dehlink et al. to the quadrature generator of Paramesh et al. and Dehlink et al. as a system design preference for serving the same function as providing I and Q local oscillator signals for converting I and Q signals.
Regarding claim 8, Paramesh et al. and Dehlink et al disclose the BFFE of claim 2 above. Paramesh et al. and Dehlink et al do not explicitly disclose wherein the combiner circuit includes a current combiner circuit configured to combine a current of converted I signal with a current of the converted Q signal. However, Chakraborty discloses a combiner circuit includes a current combiner circuit (current summers 406A-406N) configured to combine a current of converted I signal with a current of the converted Q signal (column 10, lines 25-37, figure 4 shows a current combiner in transmitter but also can be used in receiver, see column 2, line 53 – column 3, line 30). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the current combiner of Dehlink et al. to the combiner circuit of Paramesh et al. and Dehlink et al. as a system design preference for serving the same function as combining the converted I and Q signals.
Claim(s) 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al. in view of Dehlink et al. and further in view of Frounchi et al. (US 10,979,038 B2).
Regarding claim 6, Paramesh et al. and Dehlink et al disclose the BFFE of claim 4 above. Paramesh et al. and Dehlink et al do not explicitly disclose wherein the quadrature generator comprises a resistive-capacitive (RC) quadrature generator having one or more stages. However, Frounchi et al. (figures 2B and 3D) disclose a quadrature generator comprises a resistive-capacitive (RC) (200, 360) quadrature generator having one or more stages (column 6, lines 1-4; and column 8, line 16-43). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the quadrature generator comprises the RC quadrature generator having one or more stages of Frounchi et al. to the quadrature generator of Paramesh et al. and Dehlink et al. as a system design preference for serving the same function as providing I and Q local oscillator signals for converting I and Q signals.
Regarding claim 7, Paramesh et al. and Dehlink et al disclose the BFFE of claim 4 above. Paramesh et al. and Dehlink et al do not explicitly disclose wherein the quadrature generator comprises a delay line. However, Frounchi et al. (figures 2A and 3D) disclose a quadrature generator comprises a delay line (transmission lines 250a, 250 b, 326a, 326b, 327a, 327b) (column 5, lines 55-67; and column 8, line 16-43). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the quadrature generator comprises the delay line of Frounchi et al. to the quadrature generator of Paramesh et al. and Dehlink et al. as a system design preference for serving the same function as providing I and Q local oscillator signals for converting I and Q signals.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al. in view of Mu (US 10,665,958 B2).
Regarding claim 10, Paramesh et al. disclose the BFFE of claim 9 above. Paramesh et al. do not explicitly disclose wherein the first I VGA, the second I VGA, the first Q VGA, and the second Q VGA respectively comprise variable gain transconductance amplifiers having digitally controlled gains. However, Mu discloses VGAs comprise variable gain transconductance amplifiers having digitally controlled gains (column 7, line 64 – column 8, line 19). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the VGAs comprise variable gain transconductance amplifiers having digitally controlled gains of Mu to the first I VGA, second I VGA, first Q VGA, and second Q VGA of Paramesh et al. for high accuracy gain control of the VGAs.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al. in view of Saha (US 11,545,950 B2).
Regarding claim 11, Paramesh et al. disclose the BFFE of claim 1 above. Paramesh et al. do not explicitly disclose wherein the first I signal, the second I signal, the first PQ signal, and the second PQ signal each comprise current-mode differential signals. However, Saha discloses a front-end system for controlling beamforming converting RF input to I and Q current-mode differential signals (column 2, lines 17-30, column 3, lines 24-37, and column 7, line 40 – column 8, line 2). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the I and Q current-mode differential signals of Saha to the first and second I and PQ signals of Paramesh et al. as a system design preference for serving the same function as to provide I and Q signals for processing and enhancing accuracy in combining I and Q signals to generate differential output signal.
Claim(s) 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Paramesh et al. in view of Pijl et al. (US 12,119,533 B2).
Regarding claim 12, Paramesh et al. disclose the BFFE of claim 1 above. Paramesh et al. do not explicitly disclose wherein the I combiner circuit, the PQ combiner circuit, or both comprise a Wilkinson combiner. However, Pijl et al. disclose a beamforming device with Wilkinson combiner (column 17, line 56 – column 18, line 43). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the Wilkinson combiner of Pijl et al. to the I and PQ combiner circuit of Paramesh et al. for low insertion loss, high isolation and ease of fabrication.
Regarding claim 13, Paramesh et al. disclose the BFFE of claim 1 above. Paramesh et al. do not explicitly disclose wherein the BFFE is implemented within a single integrated circuit chip. However, Pijl et al. disclose a BFFE is implemented within a single integrated circuit chip (column 17, lines 39-55). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to adapt the implementing the BFFE in a single integrated circuit chip of Pijl et al. to the BFFE of Paramesh et al. for compact design.
Allowable Subject Matter
Claim 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 14, Paramesh et al. disclose the BFFE of claim 1 above. In addition, Paramesh et al. (figure 4) disclose the BFFE further comprising: the first signal chain (X1, W11, W21) being physically adjacent to the second signal chain (X1, W12, W22); a third signal chain (XN, W1N, W2N) configured to receive a third signal (XN) and comprising: a third I VGA (programmable-gain amplifier and programmable phase-shifter W1N) configured to produce a third I signal by amplifying the third signal by a third I gain value, and a third Q VGA (programmable-gain amplifier and programmable phase-shifter W2N) configured to produce a third PQ signal by amplifying the third signal by a third Q gain value, wherein the third I signal and third PQ signal are mutually in-phase, and wherein the third I gain value and third Q gain value are configured to produce a third phase shift; the I combiner circuit (lower combiner) configured to sum respective values of the first through third I signals to produce the combined I signal (Y1 signal); the PQ combiner circuit (upper combiner) configured to sum respective values of the first through third PQ signals to produce the combined PQ signal; and the converter circuit (LO Generation and upper and lower Down-converion circuits) configured to produce, based on the combined I signal and combined PQ signal, an output signal corresponding to the first through third signals respectively phase-shifted by the first through third phase shifts. However, Paramesh et al. fail to further disclose the BFFE above wherein the I combiner circuit configured to sum respective values of the first through third I signals to produce the combined I signal by: connecting the first and second I signals to an I transmission line (T-line), and combining the signal on the first I T-line with a signal corresponding to the third I signal using a first Wilkinson combiner; the PQ combiner circuit configured to sum respective values of the first through third PQ signals to produce the combined PQ signal by connecting the first and second PQ signals to a first PQ T-line, and combining the signal on the first PQ T-line with a signal corresponding to the third I signal using a second Wilkinson combiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang (US 6,456,167 B1) discloses a quadrature oscillator for generating quadrature and differential double-frequency signals is disclosed. This oscillator is formed by PMOS and NMOS transistors, complementary devices, etc.; the circuit is designed by using the differential circuit structures, two LC tanks and the technology of current reuse; it has advantages of less area requirement in circuit design, low power dissipation and low phase noise of output.
Jensen (US 8,743,914 B1) teaches an analog beamforming receiver includes a first receive element coupled with circuitry for sequentially adjusting at least one of a phase or a gain of a signal; a second receive element coupled with circuitry for sequentially adjusting at least one of a phase or a gain of the signal; a combiner coupled with the first receive element and the second receive element for combining the phase or gain adjusted signals to form a combined analog signal; and an analog to digital converter coupled with the combiner for converting the combined analog signal into digital samples.
Lee (US 9,331,632 B2) discloses an integrated circuit includes millimeter-wavelength transceiver circuitry comprising a local oscillator that generates a millimeter-wavelength oscillator signal; mixers coupled to the local oscillator; the mixers convert signals based on the millimeter-wavelength oscillator signal.
Jang (US 11,431,400 B2) teaches an apparatus and a method for generating a plurality of beamformed signals using a plurality of received signals in the wireless communication system to generate a first coupling signal by summing the plurality of the received signals and a second coupling signal corresponding to a difference of the plurality of the received signals, and a beam generator for generating a plurality of beamformed signals based on in-phase signals and quadrature-phase signals corresponding to the first coupling signal and the second coupling signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOCHIEN B VUONG whose telephone number is (571)272-7902. The examiner can normally be reached 10:00-06:00PM M-F.
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/QUOCHIEN B VUONG/Primary Examiner, Art Unit 2645