Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 12-17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Patent US 11423311-.Brothers et al (hereinafter referred to as “Brother”)
Regarding claim 1, Brother discloses a processor comprising: one or more circuits (column 4, lines 50-65) to use one or more first neural networks to generate one or more second versions of one or more second neural networks based, at least in part, on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to perform the one or more second versions of the one or more second neural networks (column 8, lines 15-50).
Regarding claim 2, Brother discloses the processor of claim 1, wherein the one or more first versions of the one or more second neural networks are compressed based, at least in part, on one or more features of one or more other hardware resources distinct from the one or more hardware resources (Fig. 2 shows one or more hardware).
Regarding claim 4, Brother discloses the processor of claim 1, wherein the generation of the one or more second versions of the one or more second neural networks is further based, at least in part, on one or more other hardware resources that are used to perform the one or more first versions of the one or more second neural networks (Fig 2).
Regarding claim 5, Brothers disclose the processor of claim 1, wherein the one or more circuits are further to update the one or more first neural networks based, at least in part, on one or more hardware features of a plurality of hardware resources, wherein the one or more hardware features comprise a numeric data type (column 3 lines 20-30, wherein modified is interpreted as updated; column 18, lines 15-25).
Regarding claim 6, Brothers disclose the processor of claim 1, wherein the one or more circuits are further to update the one or more first neural networks based, at least in part, on one or more software features of a plurality of hardware resources, wherein the one or more software features comprise development tools, runtime environment, or libraries (column 6, lines 40-55, runtime performance)
Regarding claim 7, Brother disclose the processor of claim 1, wherein the one or more circuits are further to update the one or more first neural networks based, at least in part, on one or more first software programs and one or more second software programs used to deploy one or more neural networks on different hardware resources (intended use; column 3 lines 20-30, wherein modified is interpreted as updated; column 18, lines 15-25).
Regarding claim 8, Brothers disclose the processor of claim 1, wherein the one or more circuits are further to cause one or more software programs to be performed by the one or more hardware resources, wherein the one or more second versions of one or more second neural networks are implemented in the one or more software programs (column 24, lines 50-67).
Regarding claim 9, analyses are analogous to those presented for claim 1 and are applicable for claim 9.
Regarding claim 10, analyses are analogous to those presented for claim 2 and are applicable for claim 10.
Regarding claim 12, analyses are analogous to those presented for claim 5 and are applicable for claim 12.
Regarding claim 13, analyses are analogous to those presented for claim 5 and are applicable for claim 13.
Regarding 14, Brothers disclose the method of claim 9, further comprising: modifying the one or more first neural networks based, at least in part, on one or more hardware features of plurality of hardware resources, wherein the one or more hardware features comprise number of processing units, clock speed, or memory capacity (column 6, lines 40-55, processing units).
Regarding claim 15, analyses are analogous to those presented for claim 1 and are applicable for claim 15.
Regarding claim 16, analyses are analogous to those presented for claim 2 and are applicable for claim 16.
Regarding claim 17, Brothers disclose the system of claim 15, wherein the one or more first neural networks comprise a pre-trained neural network (column 4, lines 15-20).
Regarding claim 19, analyses are analogous to those presented for claim 5 and are applicable for claim 19.
Regarding claim 20, analyses are analogous to those presented for claim 6 and are applicable for claim 20.
Claim(s) 3 and 11 rejected under 35 U.S.C. 103 as being unpatentable over Patent US 11423311- Brothers et al (hereinafter referred to as “Brother”), in view of US 20230147442 A1-Liu et al (Hereinafter referred to as “Liu”)
Regarding claim 3, Brothers disclose the processor of claim 1 (see claim 1),
Brothers fail to disclose wherein the one or more first neural networks comprise a transformer neural network.
However, in the same field of endeavor, Liu discloses wherein the one or more first neural networks comprise a transformer neural network ([0068]); one or more circuits ([0136]) to use one or more first neural networks to generate one or more second versions of one or more second neural networks based, at least in part, on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to perform the one or more second versions of the one or more second neural networks ([0104], wherein the modified neural network 502b can be generated by retraining the original neural network 502a (e.g., using a different set of training data and/or according to different training parameters), or otherwise modifying the configuration of the original neural network 502a as shown in fig. 5a)
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to modify the processor disclosed by Brothers to disclose wherein the one or more first neural networks comprise a transformer neural network as taught by Liu, to improve or enhance its performance ([0033], LIU).
Regarding claim 11, analyses are analogous to those presented for claim 3 and are applicable for claim 11.
Claim(s) 18 rejected under 35 U.S.C. 103 as being unpatentable over Patent US 11423311- Brothers et al (hereinafter referred to as “Brother”), in view of US 20230130779 A1-Jang et al (Hereinafter referred to as “Jang”).
Regarding claim 18, Brothers disclose the system of claim 15 (see claim 15),
Brothers fail to disclose wherein one or more processors are further to update the one or more first neural networks based, at least in part, on a compressed neural network that includes a plurality of versions that correspond to a plurality of hardware resources.
However, in the same field of endeavor, Jang discloses wherein one or more processors are further to update the one or more first neural networks based, at least in part, on a compressed neural network that includes a plurality of versions that correspond to a plurality of hardware resources (abstract).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to modify the processor disclosed by Brothers to disclose wherein the one or more first neural networks comprise a transformer neural network as taught by Jang, to improve or enhance its performance by efficiently storing task specific model ([0003], Jang).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LERON BECK whose telephone number is (571)270-1175. The examiner can normally be reached M-F 8 am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Czekaj can be reached at (571) 272-7327. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LERON . BECK
Examiner
Art Unit 2487
/LERON BECK/Primary Examiner, Art Unit 2487
Prosecution Insights