DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 07/17/2026. Claims 1-7, 10-14 and 17-24 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 02/19/2025 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, Invention I, species II (Fig 2B) of claims 1-2, 4-7 and 10-14, in the “Response to Election / Restriction Filed” filed on 07/17/2026 is acknowledged. This office action considers claims 1-7, 10-14 and 17-24 are thus pending for prosecution of which, non-elected claims 3 and 17-24 are withdrawn, and elected claims 1-2, 4-7 and 10-14 are examined on their merits.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites the limitation “a drain region adjacent the second side of the second drift region.” lacks proper antecedent basis. For the purpose of examination, Examiner interpreted, a drain region adjacent the second side of the drift region. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takagi (US 2004/0094811 A1; hereafter Takagi).
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Regarding claim 1. Takagi discloses an extended drain metal-oxide-semiconductor (EDMOS) field-effect transistor (FET) including an active layer that includes:
(a) a body region (Fig 1a, Si body region 22, Para [0103]) having a source-side edge (edge region 20a) and a drain-side edge (edge region 20b);
(b) a source region (source region [20a], para [0103]) adjacent the source-side edge of the body region (Fig 1a, Si body region 22, Para [0103]), the source region including at least one layer of Si (layer 13, Para [0103]) and at least one layer of a built-in voltage (Vbi) reduction material (layer 14, SiGe material, Para [0103]);
(c) a drift region (region 23, para [0103]) having a first side adjacent the drain-side edge of the body region (edge region 20b, para [0103]), and having a second side (edge region 20b, para [0103]); and
(d) a drain region (drain region [20b], para [0103]) adjacent the second side of the second drift region (region 23, para [ 0103]).
Regarding claim 2. Takagi discloses the EDMOS FET of claim 1, Takagi further discloses wherein the Vbi reduction material comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy (layer 14, Para [0103]), and/or a heterogeneous or homogenous indium arsenide alloy.
Regarding claim 4. Takagi discloses the EDMOS FET of claim 1, Takagi further discloses further including at least one body contact region (region 15, para [0103]) formed through the source region (source region 20a, para [0103]).
Regarding claim 5. Takagi discloses the EDMOS FET of claim 1, Takagi further discloses wherein the body region (Fig 1a, Si body region 22, Para [0103]) is doped with a first dopant (“ Si body region 22 containing a high concentration of the n-type impurity”), and the source region and drain region are doped with a second dopant of opposite polarity to the first dopant (“source region 20a and a drain region 20b, which contain a high concentration of a p-type impurity”, Para [ 0103]).
ALTERNATE REJECTION:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7, 10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al (US 2018/0096897 A1; hereafter Shin).
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Regarding claim 1. Shin discloses an extended drain metal-oxide-semiconductor (EDMOS) field-effect transistor (FET) including an active layer that includes:
(a) a body region (silicon substrate 100, construed as body region, Para [0055]) having a source-side edge (PW region 425) and a drain-side edge (PW region 425);
(b) a source region (source region [658, N- region [419] includes region [N+, 658]) adjacent the source-side edge (PW region 425) of the body region (substrate 100, construed as body region, Para [0055]), the source region (source region [658, N- region [419] includes region [N+, 658]) including at least one layer of N+ Si ( silicon substrate material 100, doped to form N+ region 658) and at least one layer of a built-in voltage (Vbi) reduction material (source region N-, voltage adjustment area, next to 658, Para [ 0065]);
(c) a drift region (NW region 325) having a first side adjacent the drain-side edge of the body region (PW region 425), and having a second side (NW region 325); and
(d) a drain region (drain region [D], Para [0072]) adjacent the second side of the second drift region (NW region 325).
Regarding claim 4. Shin discloses the EDMOS FET of claim 1, Shin further discloses further including at least one body contact region (P+ region 763) formed through the source region (source region [658, N- region [419]).
Regarding claim 5. Shin discloses the EDMOS FET of claim 1, Shin further discloses wherein the body region (substrate 100, construed as body region, Para [0055]) is doped with a first dopant (“ p-type ion implantation process is performed into the semiconductor substrate 100”,Para [ 0070]), and the source region and drain region are doped with a second dopant of opposite polarity to the first dopant ( N+ source/ drain”, Para [0059, 0071-0072]).
Regarding claim 7. Shin discloses the EDMOS FET of claim 1, Shin further discloses wherein the EDMOS FET is an N-type EDMOS FET (Fig 8, Para [ 0065, 0071-0072]).
Regarding claim 10. Shin discloses an N-type extended drain metal-oxide-semiconductor (NEDMOS) field-effect transistor (FET) including a Si active layer (Fig 9, nEDMOS, substrate 100, Para [0055]) that includes:
(a) a body region (silicon substrate 100, construed as body region, Para [0055]) having a source-side edge (PW region 425) and a drain-side edge (PW region 425);
(b) an N+ source region (source region [658, N- region [419] includes region [N+, 658]) adjacent the source-side edge (PW region 425) of the body region (substrate 100, Para [0055]), the N+ source region (source region [658, N- region [419]) including at least one layer of N+ Si ( silicon substrate material 100, doped to form N+ region 658) and at least one layer of an N+ built-in voltage (Vbi) reduction material (source region N-,voltage adjustment area, next to 658, Para [ 0065]);
(c) an N- drift region (NW region) having a first side adjacent the drain-side edge (PW region 425) of the body region (substrate 100, Para [0055]), and having a second side (NW region 325); and
(d) an N+ drain region (drain region [D], Para [0072]) adjacent the second side of the N- drift region (NW region 325).
Regarding claim 12. Shin discloses the NEDMOS FET of claim 10, Shin further discloses wherein the Si active layer includes a thin channel region (thin channel region between PW and NW) and abutting thick edge regions (EDGE regions PW and NW).
Regarding claim 13 Shin discloses the NEDMOS FET of claim 10, Shin further discloses further including at least one P+ body contact region (P+ region 763) formed through the N+ source region (source region [658, N- region [419]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2018/0096897 A1; hereafter Shin) as applied claims above and further in view of LIN et al (US 2016/0049464 A1; hereafter LIN).
Regarding claim 2. Shin discloses the EDMOS FET of claim 1, But Shin does not disclose explicitly wherein the Vbi reduction material comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy (layer 14, Para [0103]), and/or a heterogeneous or homogenous indium arsenide alloy.
In a similar field of endeavor, LIN discloses wherein the Vbi reduction material (source region) comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy (Para [0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Shin in light of LIN teaching “wherein the Vbi reduction material (source region) comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy (Para [0026])” for further advantage such as increase carrier mobility in the channel region and thus improves a transistor performance.
Regarding claim 11. Shin discloses the NEDMOS FET of claim 10, But Shin does not disclose explicitly wherein the Vbi reduction material (source region) comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy, and/or a heterogeneous or homogenous indium arsenide alloy.
In a similar field of endeavor, LIN discloses wherein the Vbi reduction material (source region) comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy (Para [0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Shin in light of LIN teaching “wherein the Vbi reduction material (source region) comprises at least one of germanium, a heterogeneous or homogenous silicon germanium alloy (Para [0026])” for further advantage such as increase carrier mobility in the channel region and thus improves a transistor performance.
Claims 6 and 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2018/0096897 A1; hereafter Shin) as applied claims above and further in view of Gossner et al (US 2008/0067587 A1; hereafter Gossner).
Regarding claim 6. Shin discloses the EDMOS FET of claim 1, But Shin does not disclose explicitly wherein the body region is intrinsic Si.
In a similar field of endeavor, Gossner discloses wherein the body region (substrate) is intrinsic Si (Para [0062]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Shin in light of Gossner teaching “wherein the body region (substrate) is intrinsic Si (Para [0062])” for further advantage such as high intrinsic electron and hole mobility and thus improves device performance.
Regarding claim 14. Shin discloses the NEDMOS FET of claim 10, But Shin does not disclose explicitly wherein the body region (substrate) is intrinsic Si.
In a similar field of endeavor, Gossner discloses wherein the body region (substrate) is intrinsic Si (Para [0062]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Shin in light of Gossner teaching “wherein the body region (substrate) is intrinsic Si (Para [0062])” for further advantage such as high intrinsic electron and hole mobility and thus improves device performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
