DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Moerman (US Pub. No. 2005/0240688), hereinafter referred to as Moerman, in view of Jokinen et al. (US Pub. No. 2013/0282933), hereinafter referred to as Jokinen.
Referring to claim 1 and 12, Moerman discloses a system (fig. 1), comprising: one or more processors (processed by the RX 100, [0015], fig. 1)to: receive one or more data flows (The process may begin with the transmission of a data event to the HII 122 to signal availability of new data in an output buffer, [0025]) describing a direct memory access (DMA) data movement for transferring data using a DMA device (DMA controller 136 to configure (i.e., prepare) a single DMA channel for transmission of data, [0019]); generate, based at least on the one or more data flows, a hardware-level configuration of a hardware of the DMA device for the one or more data flows (generating a transfer configuration descriptor ("TCD") comprising information pertaining to data to be transferred, [0003]; Upon receiving the data event, the HII 122 selects an appropriate CAT from the memory 128 and reads channel allocation parameters from the selected CAT (block 306, action 452). Based on this information, the HII 122 builds the TCD, [0026]); and transmit the hardware-level configuration to the DMA device for execution of the DMA data movement (After building the TCD and the TID, the HII 122 transmits the block ID, the TCD and the TID to the HTI 120 (action 458), thereby causing the HTI 120 to initiate a data transfer…various information needed by the DMA controller 136 to obtain data from the RX 100…Thus, the DMA controller 136 uses the TCD, [0027]).
While Moerman teaches the hardware-level configuration includes the use of output buffers for the one or more data flows, and the concepts of transfer bandwidth ([0014], [0018]), Moerman does not appear to explicitly disclose at least one of an input buffer bandwidth or an output buffer bandwidth.
However, Jokinen discloses configuring at least one of an input buffer bandwidth or an output buffer bandwidth (allocating space at a buffer to different DMA engines…allocation ensures that DMA engines associated with higher-bandwidth destinations are assigned more buffer space than those DMA engines associated with lower-bandwidth destinations, [0010]; size of the buffer 125 limits the rate at which the DMA engines can retrieve and forward the data segments, [0020]).
Moerman and Jokinen are analogous art because they are from the same field of endeavor, managing data transmission resources.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Moerman and Jokinen before him or her, to modify the data transfer system of Moerman to include the buffer bandwidth management of Jokinen because the bandwidth management would improve the efficiency of data transfers.
The suggestion/motivation for doing so would have been to improve overall DMA efficiency (Jokinen: [0010]).
Therefore, it would have been obvious to combine Moerman and Jokinen to obtain the invention as specified in the instant claim.
As to claims 2 and 13, Moerman discloses the generating the hardware-level configuration includes generating, based at least on the one or more data flows, an intermediate configuration, and generating, based at least on the intermediate configuration, the hardware-level configuration (The TCD comprises the information needed to complete the PaRAM entry 466. Thus, the DMA controller 136 uses the TCD to complete the PaRAM entry 466…any system event to execute the data transfer instructions contained in the PaRAM entry 466…the DMA begins retrieving data from the RX 100 as specified by the PaRAM entry 466. In this way, the DMA channel is dynamically reconfigured for each data transfer, [0027]).
As to claims 3 and 14, Moerman discloses the generating the hardware-level configuration includes allocating hardware resources of the DMA device for the one or more data flows (the DMA channel is dynamically reconfigured for each data transfer, substantially increasing data transfer efficiency, [0027]).
As to claim 4, while Moerman teaches allocating the hardware resources, use of output buffers for the one or more data flows, and the concepts of transfer bandwidth ([0014], [0018]), Moerman is silent regarding allocating input buffer bandwidth and output buffer bandwidth for the one or more data flows.
However, Jokinen discloses allocating input buffer bandwidth and output buffer bandwidth for the one or more data flows (allocating space at a buffer to different DMA engines…allocation ensures that DMA engines associated with higher-bandwidth destinations are assigned more buffer space than those DMA engines associated with lower-bandwidth destinations, [0010]; size of the buffer 125 limits the rate at which the DMA engines can retrieve and forward the data segments, [0020]).
The suggestion/motivation to combine remains as indicated above.
As to claim 5 and 15, the combination of Moerman in view of Jokinen discloses the generating the hardware-level configuration includes performing one or more optimization operations with respect to usage of bandwidth of the DMA device (Jokinen: allocating space at a buffer to different DMA engines…allocation ensures that DMA engines associated with higher-bandwidth destinations are assigned more buffer space than those DMA engines associated with lower-bandwidth destinations, [0010]; size of the buffer 125 limits the rate at which the DMA engines can retrieve and forward the data segments, [0020]). The suggestion/motivation to combine remains as indicated above.
As to claims 6 and 16, Moerman discloses the one or more data flows include phase descriptors for phases of the DMA data movement (transfer configuration descriptor ("TCD") and a transfer information descriptor ("TID")…Because a TCD and a TID is transmitted with each data transfer, the TCD and the TID enable dynamic configuration of the DMA channel through which the data blocks are transferred…thereby causing the HTI 120 to initiate a data transfer…the triggered DMA channel first transfers the TCD from the HTI 120 to a DMA parameter random-access memory ("PaRAM") entry 466…A second DMA channel then transfers the data blocks…second DMA channel triggers a third DMA channel. In turn, the third DMA channel transfers, [0024-0028]).
As to claims 7 and 17, Moerman discloses the one or more data flows include links corresponding to sequential execution of the one or more data flows (HTI 122 comprises a first-in, first-out ("FIFO") module 500. Each data transferred from an output buffer of the RX 100 to the memory 138 passes through the FIFO module, [0030]).
As to claims 8 and 18, the combination of Moerman in view of Jokinen discloses the one or more data flows include a prioritization of the one or more data flows (Jokinen: the DMA engine that is able to transfer data more quickly is given priority for shared buffer slots…changes in congestion at destinations can result in a change in the priority of slot assignments to each DMA engine, [0025-0026]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Moerman and Jokinen before him or her, to modify the data transfer system of Moerman to include the prioritization considerations of Jokinen because the prioritization would improve the efficiency of data transfers. The suggestion/motivation for doing so would have been to improve the efficiency of the DMA (Jokinen: [0026]).
As to claim 9, Moerman discloses the received one or more data flows each include a source and a destination (configure a DMA channel for data transfer, such as a source address, a data element count, and a destination address, [0026]), and the one or more processors are to determine one or more phases for the one or more data flows and links for the one or more data flows between the one or more phases (transfer configuration descriptor ("TCD") and a transfer information descriptor ("TID")…Because a TCD and a TID is transmitted with each data transfer, the TCD and the TID enable dynamic configuration of the DMA channel through which the data blocks are transferred…thereby causing the HTI 120 to initiate a data transfer…the triggered DMA channel first transfers the TCD from the HTI 120 to a DMA parameter random-access memory ("PaRAM") entry 466…A second DMA channel then transfers the data blocks…second DMA channel triggers a third DMA channel. In turn, the third DMA channel transfers, [0024-0028]).
As to claim 10 and 19, Moerman does not appear to explicitly disclose the one or more processors are to: receive one or more second data flows describing a second DMA data movement for transferring data using a second DMA device; generate, based at least on the one or more second data flows, a second hardware-level configuration for the one or more second data flows, the second hardware-level configuration corresponds to a hardware of the second DMA device; and transmit the second hardware-level configuration to the second DMA device for execution of the second DMA data movement.
However, the limitations directed to “a second DMA device” are identical to the limitations of the “a DMA device” of the parent claim, and therefore the embodiment merely duplicates the parts taught by Moerman without producing a new and unexpected result. According, the claim would have been obvious base on the teachings of Moerman because the court has held “hat mere duplication of parts has no patentable significance unless a new and unexpected result is produced” In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (see MPEP 2144.04.VI.B)
As to claim 11, Moerman discloses the one or more processors are comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system implemented using a robot; an aerial system; a medical system; a boating system; a smart area monitoring system; a system for performing deep learning operations; a system for performing simulation operations; a system for generating or presenting virtual reality (VR) content, augmented reality (AR) content, or mixed reality (MR) content; a system for performing digital twin operations; a system implemented using an edge device (fig. 1, base station); a system incorporating one or more virtual machines (VMs); a system for generating synthetic data; a system implemented at least partially in a data center; a system for performing conversational artificial intelligence (AI) operations; a system for performing generative AI operations; a system implementing language models; a system implementing large language models (LLMs); a system for hosting one or more real-time streaming applications; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; or a system implemented at least partially using cloud computing resources.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Moerman in view of Jokinen, further in view of Mienkina et al. (US Pub. No. 2022/0035953), hereinafter referred to as Mienkina.
Referring to claim 20, Moerman discloses a system comprising: one or more direct memory access (DMA) systems (fig. 1, DMA controller 136, [0019]); and one or more processors (processed by the RX 100, [0015], fig. 1) to: receive one or more data flows (The process may begin with the transmission of a data event to the HII 122 to signal availability of new data in an output buffer, [0025]) describing a DMA data movement for transferring data using the one or more DMA systems (DMA controller 136 to configure (i.e., prepare) a single DMA channel for transmission of data, [0019]); generate, based at least on the one or more data flows, a hardware-level configuration of a hardware of the one or more DMA systems for the one or more data flows (generating a transfer configuration descriptor ("TCD") comprising information pertaining to data to be transferred, [0003]; Upon receiving the data event, the HII 122 selects an appropriate CAT from the memory 128 and reads channel allocation parameters from the selected CAT (block 306, action 452). Based on this information, the HII 122 builds the TCD, [0026]); and transmit the hardware-level configuration to the one or more DMA systems for execution of the DMA data movement (After building the TCD and the TID, the HII 122 transmits the block ID, the TCD and the TID to the HTI 120 (action 458), thereby causing the HTI 120 to initiate a data transfer…various information needed by the DMA controller 136 to obtain data from the RX 100…Thus, the DMA controller 136 uses the TCD, [0027]).
While Moerman teaches the hardware-level configuration includes the use of output buffers for the one or more data flows, and the concepts of transfer bandwidth ([0014], [0018]), Moerman does not appear to explicitly disclose at least one of an input buffer bandwidth or an output buffer bandwidth. Additionally, Moerman does not appear to specifically disclose the system as a “system on chip.”
However, Jokinen discloses configuring at least one of an input buffer bandwidth or an output buffer bandwidth (allocating space at a buffer to different DMA engines…allocation ensures that DMA engines associated with higher-bandwidth destinations are assigned more buffer space than those DMA engines associated with lower-bandwidth destinations, [0010]; size of the buffer 125 limits the rate at which the DMA engines can retrieve and forward the data segments, [0020]).
Moerman and Jokinen are analogous art because they are from the same field of endeavor, managing data transmission resources.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Moerman and Jokinen before him or her, to modify the data transfer system of Moerman to include the buffer bandwidth management of Jokinen because the bandwidth management would improve the efficiency of data transfers.
The suggestion/motivation for doing so would have been to improve overall DMA efficiency (Jokinen: [0010]).
Furthermore, in a similar endeavor of managing hardware resources, Mienkina teaches integration on a system-on-chip (SOC) ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Moerman, Jokinen, and Mienkina before him or her, to implement the data transfer system of Moerman as a SoC architecture as taught by Mienkina because SoC architecture has well known advantages such as reducing physical size and weight, reducing manufacturing cost and complexity, and improving power efficiency because of reduced physical connections.
The suggestion/motivation for doing so would have been the advantages of integrated a system (Mienkina: [0013]).
Therefore, it would have been obvious to combine Moerman, Jokinen, and Mienkina to obtain the invention as specified in the instant claim.
Response to Arguments
Applicant’s arguments filed 12/30/2025 have been fully considered but are moot in view of the new ground(s) of rejection necessitated by the amendments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The Prior art of Shor et al. (US Pub. No. 2017/0171088) is pertinent to DMA buffer and bandwidth configurations.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184