Prosecution Insights
Last updated: October 27, 2026
Application No. 18/632,181

LIGHT IRRADIATION TYPE HEAT TREATMENT METHOD

Final Rejection §103
Filed
Apr 10, 2024
Priority
Feb 28, 2020 — JP 2020-033003 +2 more
Examiner
SEHAR, FAKEHA
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Screen Holdings Co., Ltd.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
86 granted / 104 resolved
+14.7% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
37 currently pending
Career history
154
Total Applications
across all art units

Statute-Specific Performance

§103
49.2%
+9.2% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
38.3%
-1.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 104 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This Office Action is in response to Applicant’s Amendment filed on September 01, 2026. Claims 1-3 have been amended. No new claims have been added. No claims have been canceled. Currently, claims 1-3 are pending. Applicant’s amendment to claims 1-3 successfully overcomes the 112(b) rejection of claims 1-3 set forth in the previous Office Action. Response to Arguments Applicant's arguments filed on August 25, 2026 have been fully considered but they are not persuasive. Regarding the information Disclosure Statement Applicant’s remarks regarding the IDS have been considered and found persuasive. The Examiner acknowledges that the striked-through references were properly submitted and considered in the parent application. Accordingly, the previous indication that these references were not considered due to their absence from the present application is withdrawn and the references have now been fully considered. Regarding the 112b rejection Applicant’s explanation of “predetermined time period” as “The “predetermined” time period is a constant time period. The preheating endures for that period and then the temperature is taken” does not align with the amended claim language. As claimed, the “predetermined period” occurs after the flash lamps and continuous lamps have been turned off. Thus, the predetermined period is not the duration of preheating but rather a predetermined elapsed time during the post-heating cooling period. In view of the amended claim language and the operation shown in Figure 13, this limitation is understood as requiring the back surface temperature of each successive dummy wafer to be measured after the same predetermined period has elapsed following termination of the heating operation. Accordingly, the 112b rejection with respect to this limitation is withdrawn. Regarding the 102 rejection The Applicant argues that, “The amended claim 1 herein makes it clear that the temperature stabilization is determined based on the back surface temperature of each of the plurality of dummy wafers at a time when a predetermined period of time has elapsed since the lamps (the flash lamps and the continuous lighting lamps) were turned off. Moreover, the temperature stabilization decision is made relative to a plurality of the dummy wafers, as indeed shown in the annotated Fig. 13 above. Respectfully, the claimed subject matter of claim 1, as amended, is not disclosed and therefore not ANTICIPATED by the teachings of Lieberer et al. In Lieberer et al., see below, there is no mention of using and confirming a plurality of dummy wafer to confirm that the preheating temperature has been stably achieved, nor the other, above mentioned, features”. The Examiner respectfully disagrees. Lieberer teaches that when starting with a cold system, each heat treatment cycle heats the wafer support plate and that the average temperature of the wafer support plate increases with each successive cycle until an equilibrium is reached. Lieberer further explains that to achieve good process repeatability the cold process chamber may be preheated to the equilibrium temperature by executing the process recipe on several preheat dummy wafers specifically stating that for example, six preheat dummy wafers can be run before the first lot is processed (see e.g., Para [0040]). Lieberer further recognizes that preheat dummy wafers may be required between lots and expressly seeks to reduce the number of dummy wafers necessary to reach the equilibrium temperature (see e.g., Paras [0041], [0042]). Lieberer shows in Figure 15, a specific preheat process in which a dummy wafer is received on a wafer support plate, temperature measurements are obtained and a preheat recipe is applied until the wafer support plate reaches a threshold temperature associated with its equilibrium temperature. Once that equilibrium condition is reached the preheat recipe is stopped and the first device wafer of the lot is loaded and processed (see e.g., Paras [0080] – [0087]). The preheat recipe of Figure 15 is linked to Lieberer’s disclosed millisecond anneal system discussed with reference to Figures 1-14, “FIG. 15 depicts a flow diagram of an example process (400) according to example embodiments of the present disclosure. The process (400) can be implemented in a millisecond anneal system, such as one of the example millisecond anneal systems discussed with reference to FIGS. 1-14.” (see e.g., Para 81). Thus, the heating and temperature measurement operations disclosed for the millisecond anneal system are applicable to the dummy wafer preheat process of Figure 15. Accordingly, Lieberer’s disclosed preheat process when read together with the millisecond anneal system, explicitly identified as implementing that process, teaches a dummy wafer subjected to a specific thermal cycle. During this cycle, the wafer is heated from the bottom using continuous lamps, subsequently flash heated at its upper surface using flash lamps and thereafter allowed to be cooled. During this thermal cycle, the system can measure the bottom surface temperature of wafer and use temperature information to determine whether the thermal system has reached a threshold associated with thermal equilibrium. As shown in Figure 1, the bulk wafer temperature varies with time during the slow cool-down represented by curve 104. Accordingly, when comparing the thermal responses of successive dummy wafers one of ordinary skill would have understood that temperatures must be evaluated at a common elapsed time following the termination of the heating operation. Doing so would ensure that the respective temperature measurements correspond to equivalent points in the cool down cycles and therefore provide a meaningful and directly comparable indication of whether the thermal condition has stabilized. The Applicant further argues that “In addition, regarding claim 3, Lieberer, et al. completely fails to disclose that processing of a product wafer begins after the maximum surface temperature of the dummy wafer in flash light irradiation becomes constant.” The Examiner respectfully disagrees. Lieberer teaches measuring the top surface temperature of the wafer during flash irradiation (see e.g., Paras [0073] – [0077]). Figure 1 also shows the rapid increase in top surface temperature caused by the flash. Lieberer further teaches using a plurality of dummy wafers to bring the chamber and wafer support plate to equilibrium before processing the first product wafer. Before equilibrium is reached successive wafers experience different thermal conditions, once equilibrium is reached the thermal conditions become repeatable (see e.g., Para [0040]). Therefore, it would have been obvious to compare the front surface flash temperatures of successive dummy wafers and determine that equilibrium has been reached when those temperatures become substantially constant. Product wafer processing could then begin. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lieberer et al. (US 2017/0194220 A1; hereafter Lieberer). Regarding claim 1, Lieberer teaches a heat treatment method of heating a substrate by irradiating the substrate with light (see e.g., Figures 1, 13 and 15), comprising: a step (a) of transporting a plurality of dummy wafers into a chamber in series before a first substrate in a lot is transported into the chamber, and placing each of the plurality of dummy wafers on a susceptor (see e.g., pre-heating of dummy wafers is performed to preheat the processing chamber to an equilibrium temperature. The process 400 includes receiving a dummy wafer on a wafer support plate in a processing chamber of a millisecond anneal system. When the wafer support plate reaches the equilibrium temperature, the process 400 includes stopping the preheat recipe; and applying a process recipe to a second substrate in the processing chamber. The process recipe is different than the preheat recipe, Paras [0042], [0043], [00045], [0082], Figure 15); a step (b) of irradiating a back surface of each of the plurality of dummy wafers disposed on the susceptor with light from continuous lighting lamps to heat the dummy wafer (see e.g., the process 400 includes heating the substrate to the intermediate temperature by using a plurality of continuous mode arc lamps. Heating the substrate to the intermediate temperature is accomplished through the bottom surface of the substrate at a ramp rate which heats the entire bulk of the wafer, Paras [0054], [0055], [0058], Figure1 and 15) and subsequently irradiating a front surface of each of the plurality of dummy wafers with a flash of light from flash lamps to heat the dummy wafer; and (see e.g., When the intermediate temperature is reached, the top side of the semiconductor substrate can be exposed to a very short, intense flash of light by a plurality of arc lamps as light sources for intense millisecond long exposure of the top surface of the substrate-the so called flash, Pars [0054], [0055], [0057], Figures 1 and 15) a step (c) of turning off the flash lamps and the continuous lighting lamps and measuring a back surface temperature of each of the plurality of dummy wafers at a time when a predetermined period of time has elapsed since the flash lamps and the continuous lighting lamps were turned off, (see e.g., Figure 13 shows the temperature measurement system for the millisecond anneal system. The temperature measurement system includes temperature sensors 152 and 154 to measure the temperature of both the top surface and the bottom surface of the wafer respectively. The readings of these temperature sensors are provided to the processor circuit. The processor circuit can be configured to process measurements obtained from the temperature sensors to determine a temperature of the semiconductor substrate and/or the wafer support plate. Curve 104 of Figure 1 represents the temperature measured during the slow cool down of the bulk of the semiconductor substrate by thermal radiation and convection with the process gas as a cooling agent. Thus, once the heating cycle is completed the bottom substrate temperature decreases, indicating that the substrate is no longer being actively heated during the cool-down portion of the cycle that is, the flash lamps and the continuous lighting lamps have been turned off, Paras [0074], [0077], [0078]) wherein the step (a) and the step (b) are repeated (see e.g., the preheat recipe is performed multiple times on different dummy wafers until the processing chamber reaches the desired temperature. Each execution of the preheat recipe includes both continuous heating and flash heating of a dummy wafer followed by a slow cool down. Accordingly, when the preheat recipe is repeated on successive dummy wafers, the continuous heating and flash heating step followed by a slow cool down are also repeated, Para [0085], Figure 15) and transporting said first substrate in the lot into the chamber and commencing processing of the first substrate in the lot (see e.g., the process 400 includes, once the processing chamber has reached equilibrium temperature, stopping the preheat recipe and loading a device substrate for processing and applying a process recipe to it in the processing chamber. The process recipe is different than the preheat recipe, Paras [0085], [0087], Figure 15) Lieberer does not explicitly teach “until a back surface temperature of the plurality of dummy wafers measured in the step (c) becomes constant”, However, Lieberer teaches that successive dummy wafers are used to bring the wafer support plate and chamber to an equilibrium condition and that before equilibrium is reached each wafer experiences a different thermal radiation background (see e.g., Para [0040]). Lieberer also teaches measuring the bottom surface temperature of the wafer using temperature sensor 154 (see e.g., Paras [0073] – [0077]). Further, Figure 1 shows that after heating the bulk temperature of the wafer undergoes a slow cool-down represented by curve 104. Thus, the back surface temperature measured during this cooling period reflects the thermal condition of the wafer as the system approaches equilibrium. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to compare corresponding back surface temperature measurements of successive dummy wafers and determine that equilibrium has been reached when those measurements become substantially constant. Regarding claim 2, Lieberer, as modified in claim 1, further teaches further comprising a step (d) of measuring a front surface achieving temperature of each of the plurality of dummy wafers at a time of flash irradiation from the flash lamps, wherein (see e.g., Figure 13 shows the temperature measurement system for the millisecond anneal system. The temperature measurement system includes temperature sensors 152 and 154 to measure the temperature of both the top surface and the bottom surface of the wafer respectively. The readings of these temperature sensors are provided to the processor circuit. The processor circuit can be configured to process measurements obtained from the temperature sensors to determine a temperature of the semiconductor substrate and/or the wafer support plate. The temperature measured by the sensor 152 during flash exposure corresponds to the claimed surface achieving temperature. Curve 112 of Figure 1 represents the rapid heating of the top surface of the semiconductor substrate during the flash exposure, Para [0054]) and subsequently, processing on the first substrate in the lot is started (see e.g., the process 400 includes, once the processing chamber has reached equilibrium temperature, stopping the preheat recipe and applying a process recipe to a second substrate in the processing chamber. The process recipe is different than the preheat recipe, Figure 15). Lieberer does not explicitly teach “the step (a) and the step (b) are repeated until both the back surface temperature measured in the step (c) and the front surface achieving temperature measured in the step (d) become constant in the plurality of dummy wafers”, However, Lieberer teaches running a preheat recipe on a number of dummy wafers before processing the first lot so that the wafer support plate/process chamber reaches an equilibrium temperature. Lieberer explains that before equilibrium is reached each substrate sees a different thermal radiation background. As the dummy wafer preheat cycles are repeated, the wafer support plate and the process chamber approach thermal equilibrium. Because the front-side temperature achieved during flash heating and the back surface temperature are both dependent on the thermal background of the chamber/support plate, these temperatures would become repeatable or constant for successive dummy wafers once equilibrium is reached. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to compare the front surface flash temperatures and back surface temperatures of successive dummy wafers and determine that equilibrium has been reached when those temperatures become substantially constant. Regarding claim 3, Lieberer teaches a heat treatment method of heating a substrate by irradiating the substrate with light (see e.g., Figures 1, 13 and 15), comprising: a step (a) of transporting a plurality of dummy wafers into a chamber in series before a first substrate in a lot is transported into the chamber, and placing each of the plurality of dummy wafers on a susceptor (see e.g., pre-heating of dummy wafers is performed to preheat the processing chamber to an equilibrium temperature. The process 400 includes receiving a dummy wafer on a wafer support plate in a processing chamber of a millisecond anneal system. When the wafer support plate reaches the equilibrium temperature, the process 400 includes stopping the preheat recipe; and applying a process recipe to a second substrate in the processing chamber. The process recipe is different than the preheat recipe, Paras [0042], [0043], [00045], [0082], Figure 15); a step (b) of irradiating a back surface of each of the plurality of dummy wafers disposed on the susceptor with light from continuous lighting lamps to heat the dummy wafer, (see e.g., the process 400 includes heating the substrate to the intermediate temperature by using a plurality of continuous mode arc lamps. Heating the substrate to the intermediate temperature is accomplished through the bottom surface of the substrate at a ramp rate which heats the entire bulk of the wafer, Paras [0054], [0055], [0058], Figure1 and 15) and subsequently irradiating a front surface of each of the plurality of dummy wafers with a flash of light from flash lamps to heat the dummy wafer; and (see e.g., When the intermediate temperature is reached, the top side of the semiconductor substrate can be exposed to a very short, intense flash of light by a plurality of arc lamps as light sources for intense millisecond long exposure of the top surface of the substrate-the so called flash, Pars [0054], [0055], [0057], Figures 1 and 15) a step (c) of measuring a front surface achieving temperature of each of the plurality of dummy wafers at a time of flash irradiation from the flash lamps, (see e.g., Figure 13 shows the temperature measurement system for the millisecond anneal system. The temperature measurement system includes temperature sensors 152 and 154 to measure the temperature of both the top surface and the bottom surface of the wafer respectively. The readings of these temperature sensors are provided to the processor circuit. The processor circuit can be configured to process measurements obtained from the temperature sensors to determine a temperature of the semiconductor substrate and/or the wafer support plate. The temperature measured by the sensor 152 during flash exposure corresponds to the claimed surface achieving temperature. Curve 112 of Figure 1 represents the rapid heating of the top surface of the semiconductor substrate during the flash exposure, Para [0054]) and subsequently, processing on the first substrate in the lot is started (see e.g., the process 400 includes, once the processing chamber has reached equilibrium temperature, stopping the preheat recipe and applying a process recipe to a second substrate in the processing chamber. The process recipe is different than the preheat recipe, Figure 15). Lieberer does not explicitly teach “wherein the step (a) and the step (b) are repeated until the front surface achieving temperature of the plurality of dummy wafers measured in the step (c) becomes constant”, However, Lieberer teaches running a preheat recipe on a number of dummy wafers before processing the first lot so that the wafer support plate/process chamber reaches an equilibrium temperature. Lieberer explains that before equilibrium is reached each substrate sees a different thermal radiation background. As the dummy wafer preheat cycles are repeated, the wafer support plate and the process chamber approach thermal equilibrium. Because the front-side temperature achieved during flash heating is dependent on the thermal background of the chamber/support plate, it would become repeatable or constant for successive dummy wafers once equilibrium is reached. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to compare the front surface flash temperatures of successive dummy wafers and determine that equilibrium has been reached when those temperatures become substantially constant. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAKEHA SEHAR whose telephone number is (571)272-4033. The examiner can normally be reached Monday-Thursday 7:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAKEHA SEHAR/ Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 10, 2024
Application Filed
Jun 11, 2026
Non-Final Rejection mailed — §103
Aug 11, 2026
Examiner Interview Summary
Aug 11, 2026
Applicant Interview (Telephonic)
Aug 25, 2026
Response Filed
Sep 30, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751074
SOURCE AND DRAIN REGIONS FOR LATERALLY ADJACENT GATE-ALL-AROUND (GAA) PMOS AND NMOS
4y 1m to grant Granted Sep 29, 2026
Patent 12740414
SEMICONDUCTOR PACKAGING
4y 4m to grant Granted Sep 15, 2026
Patent 12727390
MAGNETIC TUNNEL JUNCTION FREE LAYER OF MULTIPLE MATERIALS
3y 5m to grant Granted Sep 01, 2026
Patent 12713664
SUPERJUNCTION DEVICE AND FABRICATION METHOD THEREFOR
4y 3m to grant Granted Aug 18, 2026
Patent 12701940
METAL WIRES AND METHODS FOR MANUFACTURING THE SAME
4y 2m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+19.3%)
3y 1m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 104 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month