Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed with respect to the newly amended claims have been carefully considered but are unpersuasive. The prior rejection under 35 U.S.C. § 102 over Daeche et al. (US 7,221,048 B2) has been withdrawn and a new rejection under 35 U.S.C. § 103 over Daeche et al. alone is set forth below in view of Applicant’s amendments.
The present claims are directed strictly to an electronic package structure and not a method of manufacturing. Under well-settled patent law, product-by-process recitations in device claims impart no patentable weight unless they produce a distinct physical structure in the final article of manufacture (In re Thorpe, 777 F.2d 695).
Applicant’s arguments rely heavily on process history, asserting that the claimed lands are "formed as a protrusion of a unitary conductive substrate" and that insulating material is "molded within grooves". However, in the finished package structure, any continuous base substrate is removed, leaving behind isolated conductive metal lands embedded in insulating material. A review of FIGS. 11–13 and paragraphs (47)–(50) (see attached copy of the Daeche reference with paragraph numbers) of Daeche et al. demonstrates that the reference likewise utilizes a continuous base metal plate (29) onto which metallic passage structures (6) and contacts (14) are electrodeposited, forming a continuous metallic body prior to resin potting and subsequent plate removal. Once the continuous backing plate is removed in both manufacturing sequences, the resulting physical apparatuses are structurally indistinguishable: both consist of isolated metal lands/posts embedded in a dielectric material.
Furthermore, Applicant contends that Daeche et al.’s top rewiring structures (elements 13, 14, 37) are limited to conductive plastic. First, paragraph (14) and FIGS. 11–13 of Daeche et al. explicitly disclose metallic tracks, metallic layers, and electrodeposited metal structures. Second, even to the extent Applicant points to conductive plastic features (such as element 15 in FIG. 1), substituting a conventional plated metal pattern or copper trace for a conductive plastic layer in an electrical rewiring pathway represents an obvious substitution of known structural materials to one of ordinary skill in the art.
Because process-based manufacturing steps do not yield a structurally distinguishable final apparatus, and because material substitutions for conductive pathways are obvious, Daeche et al. alone renders the claimed package structure obvious under 35 U.S.C. § 103.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daeche et al. ( US 7221048 B2)
PNG
media_image1.png
530
816
media_image1.png
Greyscale
CLAIM 1. Daeche teaches an electronic package structure (Figs. 1 & 3), comprising:
a substrate 7 comprising:
lands laterally [6,14+8,10] spaced apart from each other, each of the lands formed as a protrusions of a unitary conductive substrate (product-by-process does not provide a clear or distinct structure. In the finished package structure of Daeche, any continuous base substrate is removed, leaving behind isolated conductive metal lands embedded in insulating material. FIGS. 11–13 and paragraphs (47)–(50) of Daeche et al. demonstrates that the reference likewise utilizes a continuous base metal plate (29) onto which metallic passage structures (6) and contacts (14) are electrodeposited, forming a continuous metallic body prior to resin potting and subsequent plate removal. Once the continuous backing plate is removed in both manufacturing sequences, the resulting physical apparatuses are structurally indistinguishable: both consist of isolated metal lands/posts embedded in a dielectric material.), the lands and comprising a conductive material, land sidewall surfaces, land top surfaces, and land bottom surfaces opposite to the land top surfaces (The land structure of Daeche implicitly has a finite 3D volume. A 3D structure having some finite 3D volume will be bounded by the recited land sidewall, top, and opposing bottom surfaces.);
an insulating material 7 disposed along the land sidewall surfaces, the insulating material being molded withing groves of the unitary conductive substrate (the product by process limitation does not provide any structural distinction from the cited prior art which molds the insulating material around the conductive lands in Figs. 11-13), wherein the insulating material comprises an insulating material top surface and an insulating material bottom surface opposite to the insulating material top surface (The insulating substrate structure of Daeche implicitly has a finite 3D volume, as do he openings where the lands are located therethrough. A 3D structure having some finite 3D volume will be bounded by the recited land sidewall, top, and opposing bottom surfaces.); and
conductive patterns 37,14,13, wherein each conductive pattern is disposed on at least a portion of a respective land top surface (Figs. 1 & 3) and comprises a plated metal pattern distinct from the conductive material of the lands (Paragraph (14) and FIGS. 11–13 of Daeche et al. explicitly disclose metallic tracks, metallic layers, and electrodeposited metal structures. Second, even to the extent Daeche points to conductive plastic features (such as element 15 in FIG. 1), substituting a conventional plated metal pattern or copper trace for a conductive plastic layer in an electrical rewiring pathway represents an obvious substitution of known structural materials to one of ordinary skill in the art. Because process-based manufacturing steps do not yield a structurally distinguishable final apparatus, and because material substitutions for conductive pathways are obvious, Daeche et al. alone renders the claimed package structure obvious to a PHOSITA); and
an electronic device 2 coupled to the conductive patterns, wherein the electronic device has opposing side surfaces in a cross-sectional view, and wherein each land is disposed laterally inward from the opposing side surfaces in the cross-sectional view (Fig. 3 – Fig. 1 demonstrates outward spaced, while Fig. 3 demonstrates the alternative of inward spacing as claimed.), wherein:
the land bottom surfaces 10 are exposed from the insulating material 7;
the land top surfaces are co-planar with the insulating material top surface (Figs. 1 & 3);
the insulating material bottom surface is disposed inward with respect to the land bottom surfaces 10 thereby exposing portions of the land sidewall surfaces below the insulating material bottom surface (Figs. 1 & 3); and
the land bottom surfaces 10 are provided without laterally overlapping onto the insulating material bottom surface (Figs. 1 & 3).
CLAIM 2. Daeche teaches the electronic package structure of claim 1, further comprising: a package body encapsulating the insulating material top surface and the electronic device, wherein the land bottom surfaces are exposed from the package body (Figs. 1 & 3).
CLAIM 3. Daeche teaches the electronic package structure of claim 2, wherein: the conductive patterns comprises a first conductive pattern comprising a first conductive pattern lateral edge; the lands comprise a first land comprising a first land sidewall; and the first conductive pattern lateral edge is coplanar with the first land sidewall in the cross-sectional view (Figs. 1 & 3).
CLAIM 4. Daeche teaches the electronic package structure of claim 1, wherein: at least one conductive pattern is laterally disposed entirely between the opposing side surfaces (Figs. 1 & 3).
CLAIM 7. Daeche teaches the electronic package structure of claim 1, wherein: the conductive patterns are disposed on portions of the insulating material 7 top surface (Figs. 1 & 3).
CLAIM 8. Daeche teaches the electronic package structure of claim 1, the lands and the insulating material together form a single-layer molded substrate; and the electronic device is directly attached to the plated metal pattern of the single-layer molded substrate. (Figs. 1 & 3 and See regarding claim 1).
CLAIM 9. Daeche teaches the electronic package structure of claim 1, wherein: the electronic device is devoid of the insulating material (Insulating material is a distinct structure from that of the electronic device).
CLAIM 10. Daeche teaches the electronic package structure of claim 1, wherein: the insulating material comprises a molded resin 30; and the insulating material 7 top surface comprises a ground (Product by Process which does not provide clear structural distinction) surface.
CLAIM 11. Daeche teaches a semiconductor package, comprising:
a single layer molded 30 substrate 7 comprising:
lands formed as protrusions of a unitary conducive substrate laterally spaced apart from each other, the lands 8,10/6,14 comprising a conductive material, land sidewalls, land top sides, and land bottom sides (Figs 1-4); a molded insulating material being molded within grooves of the unitary conductive substrate and disposed along the land sidewalls, wherein the molded insulating material comprises a molded insulating material top side and a mold material bottom side opposite to the mold material top side product-by-process does not provide a clear or distinct structure. In the finished package structure of Daeche, any continuous base substrate is removed, leaving behind isolated conductive metal lands embedded in insulating material. FIGS. 11–13 and paragraphs (47)–(50) of Daeche et al. demonstrates that the reference likewise utilizes a continuous base metal plate (29) onto which metallic passage structures (6) and contacts (14) are electrodeposited, forming a continuous metallic body prior to resin potting and subsequent plate removal. Once the continuous backing plate is removed in both manufacturing sequences, the resulting physical apparatuses are structurally indistinguishable: both consist of isolated metal lands/posts embedded in a dielectric material.); and
conductive patterns 13,14,37 adjacent to the mold material 7 top side, wherein each conductive pattern is disposed on at least a portion of a respective land top side(Figs 1-4);
first conductive bumps 24,34; and
a semiconductor device 2 directly attached to the conductive patterns disposed on the land top sides with the first conductive bumps, wherein: the semiconductor device has opposing lateral sides in a cross-sectional view (Figs 1-4);
each land is disposed laterally inward from the opposing lateral sides in the cross-sectional view; the land bottom sides are exposed from the molded insulating material; the molded insulating material bottom side is disposed inward with respect to the land bottom sides (Fig. 3 – Fig. 1 demonstrates outward spaced, while Fig. 3 demonstrates the alternative of inward spacing as claimed.); portions of the land sidewalls are exposed below the molded insulating material bottom side; and the land bottom sides are provided without laterally overlapping onto the mold material bottom side (Figs 1-4).
It is further noted, paragraph (14) and FIGS. 11–13 of Daeche et al. explicitly disclose metallic tracks, metallic layers, and electrodeposited metal structures. Second, even to the extent Daeche points to conductive plastic features (such as element 15 in FIG. 1), substituting a conventional plated metal pattern or copper trace for a conductive plastic layer in an electrical rewiring pathway represents an obvious substitution of known structural materials to one of ordinary skill in the art. Because process-based manufacturing steps do not yield a structurally distinguishable final apparatus, and because material substitutions for conductive pathways are obvious, Daeche et al. alone renders the claimed package structure obvious to a PHOSITA.
CLAIM 12. Daeche teaches the semiconductor package of claim 11, further comprising: a package body encapsulating 30 and directly contacting the molded insulating material 7 top side and the semiconductor device, wherein the land bottom sides are exposed from the package body (Figs 1-4)
CLAIM 13. Daeche teaches the semiconductor package of claim 11, wherein: the molded insulatingmaterial top side is substantially co-planar with the land top sides; and at least one conductive pattern is laterally disposed entirely between the opposing lateral sides of the semiconductor device (Figs 1-4)
CLAIM 16. Daeche teaches the semiconductor package of claim 11, wherein: the opposing lateral sides of the semiconductor device define a perimeter (Figs 1-4); a portion one of the conductive patterns is outside the perimeter (Figs 1-4); and the conductive patterns comprise a plated pattern (This limitation fails to provide structural distinction because the seed layer and plated pattern often form a monolithic, indistinguishable unit. Describing the conductive pattern by its fabrication method—rather than its physical characteristics—renders the limitation process-dependent. A plated structure is not inherently distinct from one formed by etching or deposition; thus, this describes how the device is made, not what it is. - Figs. 1 & 3).
CLAIM 17. Daeche teaches the semiconductor package of claim 11, wherein; the molded substrate is an outermost structure of the semiconductor package; and the only conductive structure embedded within the molded substrate consists of the lands (Figs 1-4).
CLAIM 18. Daeche teaches a semiconductor package, comprising:
a molded substrate comprising:
lands 6,14,8,10 laterally spaced apart from each other, the lands comprising a conductive material, land sidewalls, land top sides, and land bottom sides (Figs 1-4);
a mold material 7 disposed along the land sidewalls, wherein the mold material a mold material top side and a mold material bottom side opposite to the mold material top side (Figs 1-4); and
conductive patterns 13,14,37adjacent to the mold material top side, wherein each conductive pattern is disposed on at least a portion of a respective land top side (Figs 1-4); first conductive bumps; a semiconductor device coupled to the conductive patterns with the first conductive bumps 24 (Figs 1-4); and
a package body encapsulating 30 the mold material top side and the semiconductor device 2 (Figs 1-4),
wherein:
the semiconductor device 2 has opposing lateral sides in a cross-sectional view (Figs 1-4);
each land is disposed laterally inward from the opposing lateral sides in the cross-sectional view (Figs 1-4);
the land bottom sides 8,10 are exposed from the mold material 7 (Figs 1-4);
the land top sides are exposed from the mold material top side; the package body directly contacts portions of the land top sides exposed from the mold material top side (Figs 1-4);
the conductive patterns comprises a first conductive pattern comprising a first conductive pattern lateral edge (Figs 1-4);
the lands comprise a first land comprising a first land sidewall; and the first conductive pattern lateral edge is coplanar with the first land sidewall in the cross-sectional view (Figs 1-4).
CLAIM 19. Daeche teaches the semiconductor package of claim 18, wherein: the molded substrate comprises lands formed as protrusions of a unitary conductive substrate and the mold material is molded within grooves of the unitary conductive substrate product-by-process does not provide a clear or distinct structure. In the finished package structure of Daeche, any continuous base substrate is removed, leaving behind isolated conductive metal lands embedded in insulating material. FIGS. 11–13 and paragraphs (47)–(50) of Daeche et al. demonstrates that the reference likewise utilizes a continuous base metal plate (29) onto which metallic passage structures (6) and contacts (14) are electrodeposited, forming a continuous metallic body prior to resin potting and subsequent plate removal. Once the continuous backing plate is removed in both manufacturing sequences, the resulting physical apparatuses are structurally indistinguishable: both consist of isolated metal lands/posts embedded in a dielectric material.); the mold material bottom side is disposed inward with respect to the land bottom sides thereby exposing portions of the land sidewalls of each land (Figs 1-4); and
the land bottom sides are provided without laterally overlapping onto the mold material bottom side (Figs 1-4).
CLAIM 20. Daeche teaches the semiconductor package of claim 18, wherein: the mold material 7 top side is substantially co-planar with the land top sides (Figs 1-4); at least one conductive pattern is laterally disposed entirely between the opposing lateral sides of the semiconductor device; the mold material top side comprises a ground surface (Figs 1-4); the land top sides comprise seed layers; and the conductive patterns comprise plated patterns (This limitation fails to provide structural distinction because the seed layer and plated pattern often form a monolithic, indistinguishable unit. Describing the conductive pattern by its fabrication method—rather than its physical characteristics—renders the limitation process-dependent. A plated structure is not inherently distinct from one formed by etching or deposition; thus, this describes how the device is made, not what it is. - Figs. 1 & 3).
CLAIM 5, 14 . Daeche teaches the electronic package structure of claim 1 & 11, however may be silent upon further comprising: conductive bumps coupled to the land bottom surfaces, wherein: the conductive bumps overlap the portions of the land sidewall surfaces exposed below the insulating material bottom surface (Figs. 1 & 3).
It would however be considered a routine expectation for a PHOSITA to place conductive bumps on the bottom side of a landing pad if they are already using them on the top side for similar electrical connection purposes.
Figs 1 & 3 establish the use of bumps to bridge gaps between a landing pad and an electronic component. The claimed invention merely applies the same conductive bump technology to the bottom surface of the pad, which is a predictable variation of the top-side bonding.
The claimed overlap of the conductive bumps onto the land sidewall surfaces is a natural consequence of the solder reflow process. When solder bumps are applied to a landing pad to make contact, the heat and pressure involved in the bonding process (e.g., flip-chip assembly or thermal compression) cause the material to flow.
Solder tends to wet the side walls of a cylindrical landing pad (mushrooming effect). Therefore, designing the bump to overlap the sidewall, especially if the insulating layer is thin or slightly recessed compared to the pad surface, is a natural, expected physical outcome of standard assembly, not a unexpected result.
The use of conductive bumps is well-established in the art for creating conductive links between pads where they bridge gaps created by insulating dielectric layers to make it obvious to a POSITA to apply these techniques to the bottom of the substrate, including forming the "overlap" with the sidewall to ensure a secure, high-surface-area connection.
CLAIM 6, 15 . Daeche teaches the electronic package structure of claims 1, 11, further comprising: conductive bumps 24,34 including a first conductive bump and a second conductive bump, wherein: the electronic device comprises a semiconductor device coupled to the conductive patterns with the conductive bumps (Figs. 1 & 3); the lands comprise a first land comprising a first land top surface and a second land a second land top surface (Figs. 1 & 3);
While Daeche et al. may not explicitly disclose a single cross-sectional view showing the first and second conductive bumps simultaneously overlapping both the insulating material top surface and the first/second land top surfaces, the claimed "partial overlap" is rendered obvious by the teachings of Figures 1-4 and the associated specification. The figures in Daeche clearly illustrate conductive bumps positioned over lands that are arranged both inward and outward of the semiconductor device, explicitly showing that alignment variations are within the intended scope of the disclosure.
Simple modification of the relative alignment to achieve this specific "partial" overlap is merely a matter of design choice, failing to produce any unexpected or synergistic results. A Person Having Ordinary Skill In The Art (PHOSITA) would immediately anticipate such alignment, if not view it as inherently present in the disclosed embodiments.
When a design need—such as improved reliability or reduced package size—exists, and there are a finite number of identifiable, predictable solutions, a PHOSITA has good reason to pursue these known options within their technical grasp. Pursuing this optimization to achieve "partial overlapping" is the result of ordinary skill and common sense, not innovation, rendering the claimed subject matter obvious to a PHOSITA at the time of the invention (citing KSR Int'l Co. v. Teleflex Inc.).
14. The semiconductor package of claim 11, further comprising: second conductive bumps coupled to the land bottom sides, wherein: the second conductive bumps overlap the portions of the land sidewalls that exposed below the mold material bottom side.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/27/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
Prosecution Insights