CTNF 18/632,255 CTNF 86585 DETAILED ACTION This office action is in response to application filed on 4/10/2024. Claims 1 – 20 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 – 3, 6, 8, 13, 15 and 18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chin et al (US 20150143381, hereinafter Chin) . As per claim 1, Chin discloses: A processor comprising: one or more circuits to perform an application programming interface (API) to indicate a priority, with which to perform one or more instructions, based, at least in part, on one or more inputs to the API. (Chin [0026]: “Workload scheduler program 400 manages and schedules the tasks included in session requests received from client applications. Workload scheduler program 400 reflects the scheduling priority of tasks from the client application, given the available resources as determined by resource manager 130. Tasks are run after workload scheduler program 400 has assigned a task to a slot (resource). Workload scheduler program 400 reflects the task priority, and makes use of application programming interfaces (APIs) provided by the workload management component and supporting instructions enabling tasks to indicate when they are not actively using a resource assigned to the task.”) As per claim 2, Chin further discloses: The processor of claim 1, wherein the priority is a job priority of the one or more instructions to be performed by one or more computing resources. (Chin [0026]) As per claim 3, Chin further discloses: The processor of claim 1, wherein the one or more circuits are to perform the API to indicate one or more settings of one or more computing resources used to perform the one or more instructions based, at least in part, on the priority. (Chin [0041]) As per claim 6, Chin further discloses: The processor of claim 1, wherein the priority is to be used by one or more schedulers when scheduling the one or more instructions. (Chin [0026]) As per claim 8, it is the system variant of claim 1 and is therefore rejected under the same rationale. As per claim 13, it is the system variant of claim 6 and is therefore rejected under the same rationale. As per claim 15, it is the method variant of claim 8 and is therefore rejected under the same rationale. As per claim 18, Chin further discloses: The method of claim 15, wherein the priority with which to perform the one or more instructions is based, at least in part, on one or more indications of computing resources required to perform a job that includes the one or more instructions and a different job that includes one or more other instructions. (Chin [0041]) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chin , in view of Ramakrishnan et al (US 20210124612, hereinafter Ramakrishnan) . As per claim 4, Chin did not explicitly disclose: The processor of claim 1, wherein the priority with which to perform the one or more instructions is based, at least in part, on an estimated time required to complete performance of the one or more instructions. However, Ramakrishnan teaches: The processor of claim 1, wherein the priority with which to perform the one or more instructions is based, at least in part, on an estimated time required to complete performance of the one or more instructions. (Ramakrishnan [0015]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ramakrishnan into that of Chin in order to have the priority with which to perform the one or more instructions is based, at least in part, on an estimated time required to complete performance of the one or more instructions. Ramakrishnan [0015] has shown the claimed limitations are merely commonly known ways to determine a scheduling priority for a task, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103 . 07-21-aia AIA Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chin , in view of Suarez Garcia et al (US 20170060633, hereinafter Suarez Garcia) . As per claim 5, Chin did not explicitly disclose: wherein the priority with which to perform the one or more instructions is based, at least in part, on an estimated power consumption required to complete performance of the one or more instructions. However, Suarez Garcia teaches: wherein the priority with which to perform the one or more instructions is based, at least in part, on an estimated power consumption required to complete performance of the one or more instructions. (Suarez Garcia [0074]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Suarez Garcia into that of Chin in order to have the priority with which to perform the one or more instructions is based, at least in part, on an estimated power consumption required to complete performance of the one or more instructions. Suarez Garcia [0074] has shown the claimed limitations are merely commonly known ways to determine a scheduling priority for a task, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103 . 07-21-aia AIA Claim (s) 7, 9, 10, 14, 16, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chin , in view of Fontaine et al (US 20230093254, hereinafter Fontaine) . As per claim 7, Chin did not explicitly disclose: The processor of claim 1, wherein the one or more instructions are to be performed by one or more computing resources that are one or more portions of graphics processing units (GPUs) of a data center. However, Fontaine teaches: The processor of claim 1, wherein the one or more instructions are to be performed by one or more computing resources that are one or more portions of graphics processing units (GPUs) of a data center. (Fontaine figure 9 and [0090]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fontaine into that of Chin in order to have the one or more instructions are to be performed by one or more computing resources that are one or more portions of graphics processing units (GPUs) of a data center. One of ordinary skill in the art can recognize that that a variety of computing resources can be used to execute the tasks depending on the requirement, computing resources such as GPUs in a data center, as shown by Fontaine figure 9 and [0090], applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103. As per claim 7, Chin did not explicitly disclose: The system of claim 8, wherein the one or more instructions represent a job to be performed by one or more computing resources of a data center. However, Fontaine teaches: The system of claim 8, wherein the one or more instructions represent a job to be performed by one or more computing resources of a data center. (Fontaine figure 9 and [0090]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fontaine into that of Chin in order to have the one or more instructions represent a job to be performed by one or more computing resources of a data center. One of ordinary skill in the art can recognize that that a variety of computing resources can be used to execute the tasks depending on the requirement, computing resources such as GPUs in a data center, as shown by Fontaine figure 9 and [0090], applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103. As per claim 10, Chin further discloses: The system of claim 8, wherein the API is to indicate one or more settings of one or more [computing resource] used to perform the one or more instructions based, at least in part, on an indication of the priority. (Chin [0041]) Chin did not explicitly disclose: Wherein the one or more computing resource comprises one or more graphics processing units (GPUs); However, Fontaine teaches: Wherein the one or more computing resource comprises one or more graphics processing units (GPUs); (Fontaine figure 9 and [0090]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fontaine into that of Chin in order to have the one or more computing resource comprises one or more graphics processing units (GPUs). One of ordinary skill in the art can recognize that that a variety of computing resources can be used to execute the tasks depending on the requirement, computing resources such as GPUs in a data center, as shown by Fontaine figure 9 and [0090], applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103. As per claim 14, Chin did not explicitly disclose: The system of claim 8, wherein the one or more instructions are to be performed by one or more computing resources of a data center. However, Fontaine teaches: The system of claim 8, wherein the one or more instructions are to be performed by one or more computing resources of a data center. (Fontaine figure 9 and [0090]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fontaine into that of Chin in order to have the one or more instructions represent a job to be performed by one or more computing resources of a data center. One of ordinary skill in the art can recognize that that a variety of computing resources can be used to execute the tasks depending on the requirement, computing resources such as GPUs in a data center, as shown by Fontaine figure 9 and [0090], applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103. As per claim 16, it is the method variant of claim 9 and is therefore rejected under the same rationale. As per claim 17, it is the method variant of claim 10 and is therefore rejected under the same rationale. As per claim 20, Chin did not explicitly disclose: The method of claim 15, wherein the one or more instructions are to be performed by one or more graphics processing units (GPUs) of a cluster of GPUs. However, Fontaine teaches: The method of claim 15, wherein the one or more instructions are to be performed by one or more graphics processing units (GPUs) of a cluster of GPUs. (Fontaine figure 9 and [0090]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fontaine into that of Chin in order to have the one or more instructions are to be performed by one or more graphics processing units (GPUs) of a cluster of GPUs. One of ordinary skill in the art can recognize that that a variety of computing resources can be used to execute the tasks depending on the requirement, computing resources such as GPUs in a data center, as shown by Fontaine figure 9 and [0090], applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103 . 07-21-aia AIA Claim (s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chin , in view of McCrary et al (US 20110050713, hereinafter McCrary) . As per claim 11, Chin did not explicitly disclose: The system of claim 8, wherein the priority with which to perform the one or more instructions is based, at least in part, on one or more indications of available computing resources required to perform the one or more instructions. However, McCrary teaches: The system of claim 8, wherein the priority with which to perform the one or more instructions is based, at least in part, on one or more indications of available computing resources required to perform the one or more instructions. (McCrary [0049]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of McCrary into that of Chin in order to have the priority with which to perform the one or more instructions is based, at least in part, on one or more indications of available computing resources required to perform the one or more instructions. McCrary [0049] has shown the claimed limitations are merely commonly known ways to determine a scheduling priority for a task, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103 . 07-21-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chin , in view of Moshe et al (US 20240134696, hereinafter Moshe) . As per claim 19, Chin did not explicitly disclose: The method of claim 15, wherein the priority with which to perform the one or more instructions is based, at least in part, on first-in first-out (FIFO) job queue. However, Moshe teaches: The method of claim 15, wherein the priority with which to perform the one or more instructions is based, at least in part, on first-in first-out (FIFO) job queue. (Moshe [0053]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Moshe into that of Chin in order to have priority with which to perform the one or more instructions is based, at least in part, on first-in first-out (FIFO) job queue. Moshe [0053] has shown the claimed limitations are merely commonly known ways to determine a scheduling priority for a task, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 UCS 103 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kamenetskaya et al (US 20210103467) teaches “A graphics processing unit (GPU) may execute a shader program that may include instructions for prioritization and scheduling of waves processed in parallel. According to some aspects of the described techniques, instruction variants (e.g., set-lowest-priority, set-highest-priority, set-priority-to-N, etc.) may be executed by hardware during processing of a wave to control (e.g., modify) processing priority for that wave. As such, the described techniques for shader controlled wave scheduling priority may allow waves to be processed while avoiding interference with lagging waves, while avoiding taking resources from lagging waves, etc. In one example, when a set-lowest-priority instruction is executed by hardware during execution of a first loop of a first wave, the instruction may push the current wave's priority to be lowest on the list. Such may result in pending loops from other waves being processed prior to the processing returning to a second loop of the first wave.” Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 5712701014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHARLES M SWIFT/Primary Examiner, Art Unit 2196 Application/Control Number: 18/632,255 Page 2 Art Unit: 2196 Application/Control Number: 18/632,255 Page 3 Art Unit: 2196 Application/Control Number: 18/632,255 Page 4 Art Unit: 2196 Application/Control Number: 18/632,255 Page 5 Art Unit: 2196 Application/Control Number: 18/632,255 Page 6 Art Unit: 2196 Application/Control Number: 18/632,255 Page 7 Art Unit: 2196 Application/Control Number: 18/632,255 Page 8 Art Unit: 2196 Application/Control Number: 18/632,255 Page 9 Art Unit: 2196 Application/Control Number: 18/632,255 Page 10 Art Unit: 2196 Application/Control Number: 18/632,255 Page 11 Art Unit: 2196 Application/Control Number: 18/632,255 Page 12 Art Unit: 2196 Application/Control Number: 18/632,255 Page 13 Art Unit: 2196
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