Prosecution Insights
Last updated: July 17, 2026
Application No. 18/632,260

APPLICATION PROGRAMMING INTERFACE TO IDENTIFY PROCESSOR SETTINGS

Final Rejection §112§DP
Filed
Apr 10, 2024
Examiner
BAE, JI H
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
NVIDIA Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
636 granted / 776 resolved
+27.0% vs TC avg
Strong +21% interview lift
Without
With
+21.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
18 currently pending
Career history
801
Total Applications
across all art units

Statute-Specific Performance

§101
5.7%
-34.3% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
15.3%
-24.7% vs TC avg
§112
23.3%
-16.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 776 resolved cases

Office Action

§112 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The Examiner acknowledges Applicant’s amendments and remarks filed on 16 April 2026. They have been fully considered and are persuasive in part. The amendments are sufficient to overcome the rejections based on 35 U.S.C. 101, 102, and 103. However, they are not sufficient to overcome the rejections based on 35 U.S.C. 112(b) and the double patenting rejection. With respect to 112(b), the claims have been amended to recite circuitry “to… receive… identify… and configure”. The same reasoning applied in the prior Office Action to the original language also applies to the amended language. The amended claims recite circuitry to perform various functions. This language is indefinite because it does not specifically limit the processors in a manner that executes the functions, and may be interpreted as a non-limiting statement of intended use. This language is in contrast to suggested language that recites, for example, circuitry configured to receive, identify, configure, etc. Circuitry configured to execute functions is directed to a particular circuit that has been structurally modified to achieve those specific functions. The broadest reasonable interpretation (BRI) of circuitry “to receive”, “to identify”, or “to configure” includes circuits that may potentially be altered (for example, a generic programmable logic device) to operate in the manner claimed, but have not specifically been modified to do so. In addition to the original 112(b) rejection, Applicant’s amendments have also necessitated additional grounds for rejection under 112(b). With respect to the double patenting rejection, the amendments are not sufficient to overcome the cited reference. The most recent amendment filed in reference application no. 18/632,267 has amended its claims in the following manner: 1. (Currently Amended) One or more processors, comprising: circuitry to, in response to call: receive one or more workload characteristic inputs to the API; [[to]] identify one or more settings from a data structure that correlates the one or more workload characteristic inputs with the one or more settings; and the one or more identified settings Amended claim 1 of the ‘267 reference application is identical to amended claim 1 of the present application, with the exception that “workload characteristic” is recited instead of “clock frequency value”. However, “clock frequency value” is an obvious variant of “workload characteristic”, as shown in the rejection below. The obviousness-type double patenting rejection is therefore maintained. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites a processor comprising circuitry “to… receive… identify… configure”. This language is indefinite because it does not specifically limit the processors in a manner that executes the functions, and may be interpreted as a statement of intended use. A statement of intended use may be interpreted as non-limiting. It is therefore unclear whether a circuit “to… receive… identify… configure” refers to a specific circuit to perform the function (i.e., configured or programmed for the function) or a generic circuit that may be used to perform the function. Claim 1 recites the limitation “the API” in line 4. There is insufficient antecedent basis for this limitation. There is no prior original limitation of an API per se in the claim. Claim 1 provides an original recitation of an “API call.” Claims 8 and 15 are rejected on the same basis. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 8, and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, and 15 of copending Application No. 18/632,267 in view of Weissmann et al., U.S. Patent Application Publication No. 2017/0371399. Reference claim 1 recites one or more processors comprising: circuitry to, in response to an application programming interface (API) call: receive one or more workload characteristic inputs to the API; identify one or more settings from a data structure that correlates the one or more workload characteristic inputs with the one or more settings; and configure one or more processors to operate at one or more processor clock frequencies based, at least in part, on the one or more identified settings. Reference claim 1 does not recite receiving “one or more clock frequency value inputs” to the API. Weissmann teaches that clock frequency is a characteristic of a workload [para. 0122: “In embodiments, power control logic of a processor may dynamically determine the most efficient frequency as a function of workload scalability, workload energy consumption and platform parameters such as the amount of configured memory. Without control as described herein a long running workload may execute below the most efficient frequency, needlessly consuming too much energy.”]. It would have been obvious to one of ordinary skill in the art to combine the teachings of reference claim 1 and Weissmann by modifying reference claim 1 to receive clock frequency value inputs as suggested by Weissmann. Reference claim 1 recites workload characteristics as inputs to an API. Weissman teaches that a clock frequency can be related to workload scalability and energy consumption, indicating that it is a characteristic of the workload. The application of Weismann to reference claim 1 is motivated by Weismann’s teaching that determining the clock frequency for a workload allows that workload to run efficiently. This is a provisional nonstatutory double patenting rejection. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ganor et al., U.S. Patent Application Publication No. 2024/0211321, discloses one or more processors comprising: circuitry to, in response to an application programming interface (API) call [para. 0025: “…a user accessible API…”]: receive one or more workload characteristic inputs to the API [para. 0027: “…a user may use the API to set a 50 W maximum power consumption for a DPU… the user selected configuration may be written by the API as the non-volatile configuration file (e.g., stored on the DPU in a Bfb init file) that details specific DPU operating parameters required to achieve the user selected system budget.”]; identify one or more settings from a data structure that correlates the one or more workload characteristic inputs with the one or more settings [para. 0028: “A DPU may initially power-up with a default configuration for one or more processing and/or memory resources. The ATF may read the configuration file, as adjusted by the user through the API, from a Bfb init file to determine the power consumption limit and/or the thermal limit for the DPU (where 0 means no power consumption limit and/or no thermal limit). Thereafter, the configuration is sanitized so that the DPU cannot exceed one or more of the limits in the configuration file… The DPU may also configure the Arm clock phase locked loops (PLLs) to requested frequencies with or without facilitation by the NIC firmware.”]1; and configure one or more processors to operate at one or more processor clock frequencies based, at least in part, on the one or more identified settings [para. 0028]. Yeung et al., U.S. Patent Application Publication No. 2010/0097149, discloses one or more processors comprising: circuitry to, in response to an application programming interface (API) call [para. 0031: “…a driver for an application programming interface (API) can be included in the ROM to allow a user to provide…”]: receive one or more clock frequency value inputs to the API [para. 0031: “…explicit reference clock frequency information via a host interface…”]; identify one or more settings from a data structure that correlates the one or more clock frequency value inputs with the one or more settings [para. 0030: “…frequency selector 206 can receive estimated frequency 208 and select from among predetermined frequencies stored in memory 214 a closest frequency to send to PLL 202 via signal 210.”]2; and cause one or more processors3 to be configured to operate at one or more processor clock frequencies based, at least in part, on the one or more identified settings [Fig. 1 and 2: frequency selection 210 provided to PLL 202, which provides PLL clock to IC 102]. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office Phone: 571-272-7181 Fax: 571-273-7181 ji.bae@uspto.gov 1 Ganor’s disclosure indicates that the user provides a power consumption limit to an API which generates a configuration file associated with that limit and containing various settings, including processor frequencies. Upon subsequent reboot, the system reads the configuration file, identifies the power consumption limit, and re-configures the system according to the settings in the configuration file. 2 In the alternative embodiment discussed in para. 0031, the frequency selector employs the user-provided reference clock frequency information to select from the predetermined frequencies. 3 Yeung discloses that the PLL clock is provided within the IC rather than to one or more other processors as in claim 1.
Read full office action

Prosecution Timeline

Apr 10, 2024
Application Filed
Jan 16, 2026
Non-Final Rejection mailed — §112, §DP
Feb 06, 2026
Interview Requested
Feb 19, 2026
Applicant Interview (Telephonic)
Feb 21, 2026
Examiner Interview Summary
Apr 16, 2026
Response Filed
Jun 24, 2026
Final Rejection mailed — §112, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+21.1%)
2y 8m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 776 resolved cases by this examiner. Grant probability derived from career allowance rate.

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