The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Response to Arguments
Applicant’s arguments, see pages 5-10, filed March 9, 2026, with respect to the rejection(s) of claim(s) 1, 8, and 15 under U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of previously cited prior art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srinivasan (US Patent Application 20190384348).
As per claim 1, Srinivasan teaches one or more processors [500, fig. 1], comprising:
circuitry [110, fig. 1] to perform, in response to an application programming interface (API) call, identify one or more settings to be used to configure one or more processors to operate at one or more processor clock frequencies based, at least in part, on one or more processors to be used [0030, 0034-35, as pointed out the power manager is in communication with firmware 116 that performs API call to change the clock setting of the processor. For example, via an API, transmit a base clock frequency request to power management circuit 110 to request a change of the base clock frequency value for processor 102 and/or one or more processing cores 108. Power management circuit 110 may similarly set up processor 102 and/or one or more processing cores 108 to run at the target based clock frequency].
As per claim 2, Srinivasan teaches the one or more processors are assigned by a scheduler to perform one or more instructions in a data center [0033, fig. 2-3, time stamp specific task and set specific time required to accomplish the task. For example, the target service level may include the time required to accomplish a specific task. Thus, the target service level may be satisfied by utilizing different combinations of processing cores running at different base clock frequency values].
As per claim 3, Srinivasan teaches the API is to identify the one or more settings based, at least in part, on hardware specifications of the one or more processors to be used [0026, 0047, fig. 4, as pointed out the process of making adjustment is based on the processor characteristic from the manufacturer].
As per claim 4, Srinivasan teaches one or more indications of the one or more processors to be used are one or more inputs into the API [0029-0030, specific indicator such as thermal and so forth can be used as an indicator to make adjustment. For example, each usage scenario may specify a set of parameters including, for example, a target number of processing cores in the processor to be used, a target thermal design power (TDP), a target workload (e.g., as a percentage of the TDP), and a target reliability measurement].
As per claim 5, Srinivasan teaches the API is to identify the one or more settings based, at least in part, on one or more types of the one or more processors to be used [0051, 0084, metric determine the processor or core types].
As per claim 6, Srinivasan teaches the API is to identify the one or more settings based, at least in part, on one or more operating specifications of the one or more processors to be used [0026, 0051, manufacture and API call make determination of processor or core type].
As per claim 21, Srinivasan teaches one or more operating specifications of the one or more processors to be used [0030, as pointed out frequency and value table. For example, in one embodiment, this may be implemented as a conversion table including mappings from usages scenarios to target base clock frequency values. For example, the table may contain a list of active core counts and a corresponding base frequency value].
one or more data tables that correlate the one or more settings with the one or more processors to be used [0030, as pointed out above, specific data table can be used to make settings adjustment].
As per claims 8-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 8-20 are also anticipated by Srinivasan for the same reasons set forth in the rejected claims above.
To help with the prosecution of this application, additional rejection is given below for the independent claims
Claims 1, 8, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahmad (US Patent 12248357).
As per claim 1, Ahmad teaches one or more processors [200, fig. 2], comprising:
circuitry [210 and 215, fig. 2] to perform, in response to an application programming interface (API) call, identify one or more settings to be used to configure one or more processors to operate at one or more processor clock frequencies based, at least in part, on one or more processors to be used [col. 5 lines 37-39, col. 6 liens 20-25, fig. 4-6, as pointed, out API call can be used to make setting adjustment. For example, the TSP core 100 may support different application programming interface (API) packages. One API package employed by the TSP core 100 is an instruction API, which can be based on, e.g., Python functions that provide a conformable instruction-level TSP programming interface. Another API employed by the TSP core 100 is a tensor API, which represents a high-level application interface that supports components and tensors rather than individual instructions streaming across the TSP core 100 at particular time periods (e.g., clock cycles or compute cycles). A composite API supported by the TSP core 100 represents an API that includes both the instruction API and the tensor API. Where the controller and the power managemer make frequency and voltage adjustment as a result. For example, the controller 210 also includes circuitry to provide instructions to modify an initial clock frequency of the voltage regulator 220 and the processor 205 based on the convolution. The controller 210 supplies the instructions to the voltage regulator 220 to set the clock frequency and input voltage of the voltage regulator 220].
As per claims 8 and 15, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 8 and 15 are also anticipated by Ahmad for the same reasons set forth in the rejected claims above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VOLVICK DEROSE whose telephone number is (571)272-6260. The examiner can normally be reached on Monday-Friday 9AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571.270.1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000
/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
Prosecution Insights