DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Invention I, claims 1-12, in the reply filed on 07/14/2026 is acknowledged. The traversal is on the ground(s) that “it should be no undue burden on Examiner to consider all claims 1-20 of the application at the same time”. This is not found persuasive because as noted in the previous restriction requirement “the method of claim 13 employs a buffer layer on the first and second gate dielectric layers to mask of the region for deposition of a third dielectric layer whereas the device of claim 1 can be determined using various back etching techniques where the dielectric layer is initially uniform before masking with a buffer layer”. As such the burden still be present for the following reasons (a) the inventions have acquired a separate status in the art in view of their different classification; (b) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); and (c) the prior art applicable to one invention would not likely be applicable to another invention.
It should be noted that as in the previous requirement for restriction that “the examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined”.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yaegashi US 2009/0230460 A1.
Regarding claim 1, Yaegashi discloses:
A semiconductor device (Fig .3), comprising:
a substrate (1) comprising a first region (102), a second region (201) and a third region (202);
a first gate stack structure (HVTr) located on the substrate in the first region, wherein the first gate stack structure comprises a first gate layer (10D) and a first gate dielectric layer (2D);
a second gate stack structure (LVTr) located on the substrate in the second region, wherein the second gate stack structure comprises a second gate layer (10C) and a second gate dielectric layer (2C); and
a third gate stack structure (STr) located on the substrate in the third region, wherein the third gate stack structure comprises a third gate layer (10B) and a third gate dielectric layer (2B),
wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer, the thickness of the second gate dielectric layer is greater than a thickness of the third gate dielectric layer,
wherein thicknesses of the first gate layer and the second gate layer are respectively
greater than a thickness of the third gate layer.
Regarding claim 2, Yaegashi discloses:
wherein: the first gate layer comprises a first gate conductive layer (6D/7D; TaN/NiSi) and a first buffer layer (5D poly), wherein the first buffer layer is between the first gate conductive layer and the first gate dielectric layer; and
the second gate layer comprises a second gate conductive layer (6C/7C; TaN/NiSi) and a second buffer layer (5C poly), wherein the second buffer layer is between the second gate conductive layer and the second gate dielectric layer.
Regarding claim 3, Yaegashi discloses:
wherein resistances of the first buffer layer and the second buffer layer are higher than those of the first gate conductive layer and the second gate conductive layer (poly vs. TaN/NiSi).
Regarding claim 4, Yaegashi discloses:
wherein the first buffer layer and the second buffer layer are made of materials comprising doped polycrystalline silicon or silicon oxide (para 0072 and 0077).
Allowable Subject Matter
Claims 5-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claim 5 stating “the height of the top surface of the first gate layer is equal to a height of a top surface of the second gate layer”; and of claim 9 stating “wherein a height of a top surface of the third gate layer is equal to a height of a top surface of the first gate layer, and is equal to a height of a top surface of the second gate layer”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
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