Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/11/2024, 08/08/2024, and 02/02/2026 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, and 8-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nelson, Cory US 20220346222 A1 .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Nelson teaches:
A circuit board comprising:
a circuit board substrate (407) having a mounting surface (404); and
a single layer capacitor (402) at least partially embedded within the circuit board
substrate, the single layer capacitor comprising:
a substrate (402) having a first surface opposite a second surface,
a first conductive layer (106) formed over at least a portion of the first
surface, and
a second conductive layer (408) formed over at least a portion of the
second surface,
wherein at least one of the first conductive layer or the second
conductive layer has a thickness that is at least about 5 microns. (para 38)
See figures 4A and 4B
2. The circuit board of claim 1, wherein both the first conductive layer
and the second conductive layer have a thickness that is at least about 10
microns. (para 38)
3. The circuit board of claim 1, further comprising:
at least one via (412) connected with the first conductive layer, the at least one via (412) extending toward the mounting surface (404) of the circuit board substrate (407). Figures 4A and 4B
4. The circuit board of claim 3, wherein a circuit board conductive layer (414)
is formed over the mounting surface (404), and wherein the at least one via (412) electrically connects the circuit board conductive layer (414) and the first conductive (414) layer of the single layer capacitor (402). Figures 4A and 4B
5. The circuit board of claim 1, wherein the single layer capacitor is fully
embedded within the circuit board substrate such that the substrate, the first
conductive layer, and the second conductive layer are each positioned below the
mounting surface along a height direction. (Figure 4A)
6. The circuit board of claim 1, wherein the single layer capacitor is fully
embedded within the circuit board substrate such that the first conductive layer is
co-planar with the mounting surface. (figure 4B)
8.
A single layer capacitor comprising:
a substrate (402) having a first surface and a second surface opposite the first
surface;
a first conductive layer (106) formed over at least a portion of the first surface of
the substrate; and
a second conductive layer (408) formed over at least a portion of the second
surface of the substrate,
wherein at least one of the first conductive layer or the second conductive
layer has a thickness that is at least about 5 microns. (para 38) Figure 4A and 4B
9. The single layer capacitor of claim 8, wherein both the first
conductive layer and the second conductive layer have a thickness that is at least about 10 microns. (para 38)
10. A method of forming a single layer capacitor, the method comprising:
depositing a first conductive layer (106) over at least a portion of a first surface of a substrate (402); and
depositing a second conductive layer (408) over at least a portion of a second
surface of the substrate (402), the second surface opposite the first surface,
wherein at least one of the first conductive layer or the second conductive
layer has a thickness that is at least about 5 microns. (para 48) Figures 4A and 4B
11. The method of claim 10, wherein both the first conductive layer and
the second conductive layer have a thickness that is at least about 10 microns. (para 38)
12. The method of claim 10, wherein depositing the first conductive layer
comprises screen printing the first conductive layer over at least the portion of the
first surface of the substrate such that the first conductive layer has a thickness
that is at least about 5 microns. (para 38)
13. The method of claim 10, wherein depositing the second conductive
layer comprises screen printing the second conductive layer over at least the
portion of the second surface of the substrate such that the second conductive
layer has a thickness that is at least about 5 microns. (para 38 and 55)
14. The method of claim 10, wherein depositing the first conductive layer
comprises printing a first layer of conductive material over at least the portion of
the first surface of the substrate and plating at least one additional layer of
conductive material over the first layer of conductive material. (para 54 and 55)
15. The method of claim 14, wherein depositing second first conductive
layer comprises printing a second layer of conductive material over at least the
portion of the second surface of the substrate and plating at least one additional
layer of conductive material over the second layer of conductive material. (para 54 and 55)
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 8-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20100003060 A,
‘060 teaches:
A circuit board comprising:
a circuit board substrate (140,150) having a mounting surface (not labeled Figure 2b); and
a single layer capacitor (160) at least partially embedded within the circuit board
substrate (140,150), the single layer capacitor comprising:
a substrate (110) having a first surface opposite a second surface,
a first conductive layer (120) formed over at least a portion of the first
surface, and
a second conductive layer (130) formed over at least a portion of the
second surface,
wherein at least one of the first conductive layer or the second
conductive layer has a thickness that is at least about 5 microns.
‘060 does teach:
wherein the upper electrode 20 and the lower electrode 30 mainly use copper foil having a thickness of 10 to 50 μm. (conventional art Figure 1B and machine translation)
2. The circuit board of claim 1, wherein both the first conductive layer
and the second conductive layer have a thickness that is at least about 10
microns. (conventional art Figure 1B and machine translation)
3. The circuit board of claim 1, further comprising:
at least one via (370) (Figure 4) connected with the first conductive layer (102), the at least one via (370) extending toward the mounting surface (not labeled) of the circuit board substrate (140,150). Figure 4
4. The circuit board of claim 3, wherein a circuit board conductive layer (380)
is formed over the mounting surface (not labeled), and wherein the at least one via (370) electrically connects the circuit board conductive layer (380) and the first conductive (320) layer of the single layer capacitor (360). Figure 4
5. The circuit board of claim 1, wherein the single layer capacitor (160) is fully
embedded within the circuit board substrate (140,150) such that the substrate, the first conductive layer (120), and the second conductive layer (130) are each positioned below the mounting surface along a height direction. (Figure 4)
6. The circuit board of claim 1, wherein the single layer capacitor (160) is fully
embedded within the circuit board substrate (140,150) such that the first conductive layer (120) is co-planar with the mounting surface. (figure 4)
8.
A single layer capacitor comprising:
a substrate (10) having a first surface and a second surface opposite the first
surface;
a first conductive layer (20) formed over at least a portion of the first surface of
the substrate (10); and
a second conductive layer (30) formed over at least a portion of the second
surface of the substrate (10),
wherein at least one of the first conductive layer or the second conductive
layer has a thickness that is at least about 5 microns.
‘060 teaches wherein the upper electrode 20 and the lower electrode 30 mainly use copper foil having a thickness of 10 to 50 μm. ( conventional art Figure 1B and machine translation)
9. The single layer capacitor of claim 8, wherein both the first
conductive layer and the second conductive layer have a thickness that is at least about 10 microns. (conventional art Figure 1B and machine translation)
10. A method of forming a single layer capacitor, the method comprising:
depositing a first conductive layer (20) over at least a portion of a first surface of a substrate (10); and
depositing a second conductive layer (30) over at least a portion of a second
surface of the substrate (10), the second surface opposite the first surface,
wherein at least one of the first conductive layer (20) or the second conductive layer (30) has a thickness that is at least about 5 microns.
‘060 teaches wherein the upper electrode 20 and the lower electrode 30 mainly use copper foil having a thickness of 10 to 50 μm. ( conventional art Figure 1B and machine translation)
11. The method of claim 10, wherein both the first conductive layer and
the second conductive layer have a thickness that is at least about 10 microns. ( conventional art Figure 1B and machine translation)
12. The method of claim 10, wherein depositing the first conductive layer
comprises screen printing the first conductive layer over at least the portion of the
first surface of the substrate such that the first conductive layer has a thickness
that is at least about 5 microns. ( conventional art Figure 1B and machine translation)
13. The method of claim 10, wherein depositing the second conductive
layer comprises screen printing the second conductive layer over at least the
portion of the second surface of the substrate such that the second conductive
layer has a thickness that is at least about 5 microns. (description of embodiments, machine translation)
14. The method of claim 10, wherein depositing the first conductive layer
comprises printing a first layer of conductive material over at least the portion of
the first surface of the substrate and plating at least one additional layer of
conductive material over the first layer of conductive material. (description of embodiments, machine translation)
15. The method of claim 14, wherein depositing second first conductive
layer comprises printing a second layer of conductive material over at least the
portion of the second surface of the substrate and plating at least one additional
layer of conductive material over the second layer of conductive material. (description of embodiments, machine translation)
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach:.
7. The circuit board of claim 1, wherein the single layer capacitor is
partially embedded within the circuit board substrate such that one or more of the
substrate, the first conductive layer, or the second conductive layer extends above the mounting surface along a height direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. McGregor et al, US 20070139901 A1 in view of Sylvester et al, US 20040012938 A1 also teaches the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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