DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Tittle
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The Tittle does not contain “a circuit board including a single layer capacitor”. Please, revise.
The following title is suggested: SINGLE LAYER CAPACITOR AND CIRCUIT BOARD INCLUDES A SINGLE LAYER CAPACITOR.
Abstract
The abstract of the disclosure is objected to because:
In line 1, please, change “Single layer capacitors and circuit boards” to - - Single layer capacitor and circuit board - - because none of figures that show “Single layer capacitors and circuit boards” in any figures. Please, revise.
In lines 1, 4, and 8, the phrase of “can” is not understood because the term “can” recites to a broad range or limitation followed by linking terms and a narrow range or limitation within the broad range or limitation is considered indefinite since the resulting claim does not clearly set forth the metes and bounds of the patent protection desired.
Please, change “can include” to - - includes - - for proper reading.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 2-4 are objected to because of the following informalities:
Regarding claims 2-3, line 1, before “the single layer capacitor” please, insert - -wherein - - for proper reading.
Regarding claim 4, line 1, please, change “wherein a circuit board conductive layer” to - - further comprising a circuit board conductive layer - -.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-15 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Tung (U.S. 2004/0128822) hereafter Tung.
As to claim 1, Tung discloses a circuit board (400 as shown in figures 2-5 comprising:
a circuit board substrate (the body of the circuit board 400, figure 4) having a mounting surface; and
a single layer capacitor (25) at least partially embedded within the circuit board
substrate (the capacitor 25 embedded into the core board 21 or the body 400), the single layer capacitor (25) comprising:
a substrate (the body of the capacitor 25) having a first surface (top surface) opposite a second surface (bottom surface),
a first passivation layer (the top resistive film 23) formed over at least a portion of the first surface (top surface) of the substrate,
a first conductive layer (the top conductive foil 22) formed over at least a portion of the first passivation layer, and
a second conductive layer (the bottom conductive foil 22) formed over at least a portion of the second surface of the substrate.
As to claim 2, Tung discloses the single layer capacitor (25) further comprising: a second passivation layer (the bottom resistive film 23) formed over at least a portion of the second surface (the bottom surface) of the substrate,
wherein the second conductive layer (the bottom conductive foil 22) is formed over the second passivation layer (the bottom resistive film 23) such that the second passivation layer is disposed between the substrate and the second conductive layer.
As to claim 3, Tung discloses the single layer capacitor further comprising: at least one via (not label but shown in figure 4) connected with the first conductive layer, the at least one via extending toward the mounting surface (top surface) of the circuit board substrate.
As to claim 4, Tung further comprising a circuit board conductive layer (the plated through via or a circuit layer 41, figure 4) is formed over the mounting surface, and wherein the at least one via electrically connects the circuit board conductive layer (the plated 41) and the first conductive layer (the top 22) of the single layer capacitor (25).
As to claim 5, Tung discloses the single layer capacitor (25) is fully embedded within the circuit board substrate (figure 4) such that the substrate, the first passivation layer (23), the first and second conductive layers (22) are each positioned below the mounting surface along a height direction.
As to claim 7, Tung discloses the single layer capacitor (25) as shown in figure 5 is partially embedded within the circuit board substrate (500) such that one or more of the substrate, the first passivation layer (23), the first or second conductive layer (22) extends above the mounting surface along a height direction.
As to claim 8, Tung discloses a single layer capacitor (25) as shown in figures 2-4 comprising:
a substrate (the body of the capacitor 25) having a first surface (top surface) opposite a second surface (bottom surface),
a first passivation layer (the top resistive film 23) formed over at least a portion of the first surface (top surface) of the substrate,
a first conductive layer (the top conductive foil 22) formed over at least a portion of the first passivation layer, and
a second conductive layer (the bottom conductive foil 22) formed over at least a portion of the second surface of the substrate.
As to claim 9, Tung discloses the single layer capacitor (25) further comprising: a second passivation layer (the bottom resistive film 23) formed over at least a portion of the second surface (the bottom surface) of the substrate,
wherein the second conductive layer (the bottom conductive foil 22) is formed over the second passivation layer (the bottom resistive film 23) such that the second passivation layer is disposed between the substrate and the second conductive layer.
As to claim 10, Tung discloses a method for forming a single layer capacitor (25) as shown in figures 2-4, the method comprising:
depositing a first passivation layer (top element 23) over at least a portion of a first surface of a substrate (the body of the capacitor 25);
depositing a first conductive layer (top element 22) over at least a portion of the first passivation layer (the top element 23); and
depositing a second conductive layer (the bottom element 22) over at least a portion of a second surface of the substrate, the second surface opposite the first surface.
As to claim 11, Tung discloses depositing a second passivation layer (the bottom element 23) over at least a portion of the second surface (the bottom surface) of the substrate such that the second passivation layer (23) is disposed between the second surface of the substrate and the second conductive layer.
As to claim 12, Tung discloses the first and second passivation layers (23) are deposited before depositing either of the first conductive layer (22) or the second conductive layer (22), and wherein depositing the first passivation layer and depositing the second passivation layer comprises depositing a paste and firing the substrate with the paste deposited thereon.
As to claim 13, Tung discloses depositing the second conductive layer (22) comprises plating the second conductive layer (22) on the second passivation layer.
As to claim 14, Tung discloses depositing the first passivation layer (23) comprises depositing a paste and firing the substrate with the paste deposited
thereon.
As to claim 15, Tung discloses depositing the first conductive layer (22) comprises plating the first conductive layer on the first passivation layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung in view of Lai et al. (U.S. 2014/0076492).
Regarding claim 6, Tung discloses the single layer capacitor (25) is fully embedded within the circuit board substrate (400 or 500) except for the first conductive layer is co-planar with the mounting surface.
Lai teaches a package substrate having embedded capacitor(s) (23) as shown in figure 2C comprising the single layer capacitor (23) is fully embedded within the circuit board substrate (20) except for the first conductive layer (230a or 230b) is co-planar with the mounting surface.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Lai employed in the circuit board of Tung in order to provide high density mounting and reduce size for the component(s) embedded within the body of the circuit board.
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/TUAN T DINH/Primary Examiner, Art Unit 2848