DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-14, and 17 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Kuwako et al. (U.S. Patent 9,924,597).
As to claim 1, Kuwako discloses a circuit board (20) as shown in figures 3-5 comprising:
a circuit board substrate (the body of the laminate 20) having a mounting surface; and
a single layer capacitor (10) at least partially embedded within the circuit board substrate (20), the single layer capacitor (10) comprising:
a substrate (2) having a first surface (top surface) opposite a second surface (bottom surface),
a first passivation layer (top element 4) formed over at least a portion of the first surface of the substrate (2),
a first conductive layer (top element 3) plated over at least a portion of the first passivation layer (4), and
a second conductive layer (bottom element 3) formed over at least a portion of the second surface of the substrate (2).
As to claim 2, Kuwako discloses the single layer capacitor (10) further comprises:
a second passivation layer (bottom element 4) formed over at least a portion of the second surface of the substrate (2),
wherein the second conductive layer (3) is plated over the second passivation layer (4) such that the second passivation layer (4) is disposed between the substrate and the second conductive layer (3).
As to claim 3, Kuwako discloses the single layer capacitor further comprising comprises:
at least one via (6) connected with the first conductive layer (3), the at least one via (6) extending toward the mounting surface of the circuit board substrate.
As to claim 4, Kuwako further comprising: a circuit board conductive layer (7) formed over the mounting surface,
wherein the at least one via (6) electrically connects the circuit board conductive layer (7) and the first conductive layer (3) of the single layer capacitor (10), see figures 5-6.
As to claim 5, Kuwako discloses the single layer capacitor (10) is fully embedded within the circuit board substrate (20) such that the substrate (2), the first passivation layer (4), the first conductive layer (3), and the second conductive layer (3) are each positioned below the mounting surface along a height direction.
As to claim 8, Kuwako discloses a single layer capacitor (10) as shown in figures 3-5 comprising:
a substrate (2) having first surface and a second surface opposite the first surface;
a first passivation layer (top element 4) formed over at least a portion of the first surface of the substrate;
a first conductive layer (top element 3) plated over at least a portion of the first passivation layer (4); and
a second conductive layer (bottom element 3) formed over at least a portion of the second surface of the substrate (2).
As to claim 9, Kuwako further comprising: a second passivation layer (bottom element 4) formed over at least a portion of the second surface of the substrate, wherein the second conductive layer (3) is formed plated over the second passivation layer (4) such that the second passivation layer (4) is disposed between the substrate (2) and the second conductive layer (3).
As to claim 10, Kuwako discloses a method for forming a single layer capacitor (10) as shown in figures 3-4, the method comprising:
depositing a first passivation layer (4) over at least a portion of a first surface (top surface) of a substrate (2);
plating (column 11, line 4+) a first conductive layer (top element 3) over at least a portion of the first passivation layer (top element 4); and depositing a second conductive layer (bottom element 3) over at least a portion of a second surface (bottom surface) of the substrate (2), the second surface opposite the first surface.
As to claim 11, Kuwako further comprising:
depositing a second passivation layer (bottom element 4) over at least a portion of the second surface of the substrate (2) such that the second passivation layer (4) is disposed between the second surface (the bottom surface) of the substrate (2) and the second conductive layer (3).
As to claim 12, Kuwako discloses the first and second passivation layers (4) are deposited before depositing either of the first conductive layer (3) or the second conductive layer (3), and wherein depositing the first passivation layer (4) and depositing the second passivation layer (4) comprises depositing a paste and firing the substrate (2) with the paste deposited thereon.
As to claim 13, Kuwako discloses depositing the second conductive layer (3) comprises plating the second conductive layer (3) on the second passivation layer (4).
As to claim 14, Kuwako discloses depositing the first passivation layer (dielectric resin layer 4) comprises depositing a paste and firing the substrate (2) with the paste deposited thereon.
As to claim 17, Kuwako discloses the first passivation layer (4) is formed from a polymer material (epoxy-based resin material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuwako in view of Lai et al. (U.S. 2014/0076492).
Regarding claim 6, Kuwako discloses all of the limitations of claimed invention except for the single layer capacitor is fully embedded within the circuit board substrate such that the first conductive layer is co-planar with the mounting surface.
Lai teaches a package substrate having embedded capacitor(s) (23) as shown in
figure 2C comprising the single layer capacitor (23) is fully embedded within the circuit
board substrate (20) except for the first conductive layer (230a or 230b) is co-planar
with the mounting surface.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Lai employed in the circuit board of Tung in
order to provide high density mounting and reduce size for the component(s) embedded
within the body of the circuit board.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuwako in view of Tung (‘822).
Regarding claim 7, Kuwako discloses the single layer capacitor is partially embedded within the circuit board substrate and some all of the limitation of claimed invention except for one or more of the substrate, the first passivation layer, the first conductive layer, or the second conductive layer extends above the mounting surface along a height direction.
Tung discloses the single layer capacitor (25) as shown in figure 5 is partially embedded within the circuit board substrate (500) such that one or more of
the substrate, the first passivation layer (23), the first or second conductive layer (22)
extends above the mounting surface along a height direction.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Tung employed in the circuit board of Tung in order to provide external electrical connections.
Regarding claim 16, Kuwako discloses all of the limitations of claimed invention except for the first conductive layer has a first thickness along a height direction, the first passivation layer has a first passivation thickness along the height direction, the second conductive layer has a second thickness along the height direction, and the substrate has a substrate thickness along the height direction, and wherein a ratio of the substrate thickness to a sum of the first thickness, the first passivation thickness, and the second thickness is at least 1.
Tung teaches in figures 4-5 comprising the first conductive layer (top foil 22) has a first thickness along a height direction, the first passivation layer (top resistive film 23) has a first passivation thickness along the height direction, the second conductive layer (bottom foil 22) has a second thickness along the height direction, and the substrate (the body) has a substrate thickness along the height direction, and wherein a ratio of the substrate thickness to a sum of the first thickness, the first passivation thickness, and the second thickness is at least 1.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Tung employed in the circuit board of Tung in order to provide high density mounting and reduce size for the component(s) embedded
within the body of the circuit board.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuwako in view of Hsu et al. (U.S. 2012/0168217).
Regarding claim 18, Kuwako discloses all of the limitations of claimed invention except for the first passivation layer is formed from a ceramic material.
Hsu teaches embedded capacitor substrate module as shown in figure 2A comprising the first passivation layer (122-1 or 122-2) is formed from a ceramic material (aluminum oxide layer, para-0022+).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Hsu employed in the circuit board of Tung in order to provide excellent store electrical energy characteristic.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14, and 16-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T DINH/Primary Examiner, Art Unit 2847
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