Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/11/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,9,10-11,17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al, US 20230361086 A1.
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Pertaining to claim1, Chen ( see fig.12 above) teaches A semiconductor package comprising: a package substrate[210]; and at least two semiconductor chips[X1 and X2] stacked on the package substrate and electrically connected to the package substrate[210] via a wire, wherein a first semiconductor chip[X1] located on a lower side among the at least two semiconductor chips is coupled, without an adhesive, to a second semiconductor chip [X2] located above the first semiconductor chip[X1] ( see also para 0056 talking about bonding the semiconductor chips without using adhesive layers).
Pertaining to claim 9, Chen ( see fig.12 above) The semiconductor package of claim 1, wherein the semiconductor package has one of: a thickness less than that of a first semiconductor package comprising an adhesive by a thickness of the adhesive, and a thickness that is substantially the same thickness as the first semiconductor package, with each of the at least two semiconductor chips[X1 and X2] being thicker than a semiconductor chip of the first semiconductor package.
Pertaining to claim10, Chen ( see fig.12 above) The semiconductor package of claim 1, wherein a semiconductor chip [X1] that is lowermost among the at least two semiconductor chips[X1 and X2] is bonded to the package substrate[210] with an adhesive [AF].
Pertaining to claim11, Chen ( see fig.12 above) The semiconductor package of claim 1, wherein the at least two semiconductor chips [X1 and X2] are stacked in a step shape or zigzag shape on the package substrate[210].
Pertaining to claim17, Chen ( see fig.12 above) A semiconductor package comprising: a package substrate[210]; and at least two semiconductor chips[X1 and X2] stacked on the package substrate [210] and each having an upper surface and a lower surface having rectangular shapes ( by virtue of the shape) , wherein the upper surface of each of the at least two semiconductor chips comprises an active surface and the lower surface of each of the at least two semiconductor chips comprises a non-active surface, and chip pads [upper edge BP1] are arranged in a first direction on the upper surface of each of the at least two semiconductor chips[X1 and X2], the chip pads [upper edge BP1] are adjacent to a first edge that corresponds to one line of the rectangular shapes of the upper and lower surfaces of each of the at least two semiconductor chips [X1 and X2] and extend in the first direction, wherein the at least two semiconductor chips[X1 and X2] are stacked on each other such that the chip pads [upper edge BP1] thereof are exposed to the outside, and the chip pads [upper edge BP1] are electrically connected to substrate pads [220] of the package substrate[210] via wires[Wx], and wherein a first semiconductor chip[X1] located on a lower side among the at least two semiconductor chips [X1 and X2] is coupled, without an adhesive ( see para 0056), to a second semiconductor chip [X2] located above the first semiconductor chip[X1].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230361086 A1. In view of Uzoh et al, US 20230207474 A1.
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Pertaining to claim 7 and 20, Chen ( see fig.12 above) teaches The semiconductor package of claim 1 or 17, but is silent wherein a semiconductor chip that is lowermost among the at least two semiconductor chips is bonded to the package substrate without an adhesive.
However, in the same field on endeavor , Uzoh ( see Uzo fig.9B above) teaches wherein a semiconductor chip [9a] that is lowermost among the at least two semiconductor chips[9a and 9b] is bonded to the package substrate[10] without an adhesive ( see para 0026). In view of Uzoh, it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Uzoh into that of Chen for a direct bonding between the lower semiconductor chip and the package substrate for an improved packaging structure.
Allowable Subject Matter
Claims12-16 allowed.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Chen et al, US 20230361086 A1 teaches the limitation of " a) obtaining a semiconductor substrate having i) a bulk semiconductor and ii) a surface oxide layer over the bulk semiconductor; b) dry-etching the substrate with a fluorine containing species to remove the surface oxide layer and thereby expose a surface of the bulk semiconductor; and then d) then epitaxially depositing a semiconductor layer on the surface of the bulk semiconductor, but it does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 1 including “”
Claims 2-6,8,18-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest prior art of record of Chen et al, US 20230361086 A1 teaches the limitation of claim 1, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 2 including “wherein: each of the at least two semiconductor chips has an upper surface and a lower surface having rectangular shapes, and the upper surface comprises an active surface and the lower surface comprises a non-active surface, chip pads are arranged in a first direction on the upper surface of each of the at least two semiconductor chips, the chip pads are adjacent to a first edge that corresponds to one line of the rectangular shapes of the upper and lower surfaces of each of the at least two semiconductor chips and extend in the first direction, an alignment pattern line is formed on the upper surface of the first semiconductor chip and extends parallel to the first edge of the upper surface of the first semiconductor chip, and the first edge of the lower surface of the second semiconductor chip is self-aligned with the alignment pattern line of the first semiconductor chip.” in combination with the remaining limitations of the claim.
The closest prior art of record of Chen et al, US 20230361086 A1 teaches the limitation of claim 7, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 8 including “wherein the lowermost semiconductor chip is disposed on a solder resist (SR) open region of the package substrate, and wherein the SR open region is formed by removing a portion of an SR layer on an upper surface of the package substrate. “ in combination with the remaining limitations of the claim.
The closest prior art of record of Chen et al, US 20230361086 A1 teaches the limitation of claim 17, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 18 including “further comprising an alignment pattern line formed on the upper surface of the first semiconductor chip, the alignment pattern line extends parallel to the first edge of the upper surface of the first semiconductor chip, wherein the first edge of the lower surface of the second semiconductor chip is self- aligned with the alignment pattern line of the first semiconductor chip” in combination with the remaining limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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