DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 04/11/2024 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0095830 A1, hereinafter “Kim”).
In regards to claim 1, Kim discloses (See, for example, Figs. 3 and 4) a semiconductor device, comprising:
a first cell adjacent to a second cell (“the logic cell LC may include a first cell boundary CB1 that extends in the second direction D2. On a location opposite to that of the first cell boundary CB1, a second cell boundary CB2 may be defined to extend in the second direction D2.” See Par [0075]; and “the first power line POR1 may be provided on the first cell boundary CB1, the second power line POR2 may be provided on the second cell boundary CB2.”, See par [0077]; logic cell LC with cell boundaries CB1 and CB2);
the first cell including first stacked source/drain regions on at least two levels (“The substrate 100 may be provided thereon with the first active region AR1 as a bottom tier, and the first active region AR1 may be provided thereon with the second active region AR2 as a top tier.”, See Par [0028]; “The active pattern AP may be provided thereon with the first active region AR1 that includes first channel patterns CH1 and first source/drain patterns SD1.”, See Par [0037]; and “The second active region AR2 may include second channel patterns CH2 and second source/drain patterns SD2.”, See Par [0045]; SD1 on the bottom tier within the first active region AR1, and SD2 on a top tier within second active region AR2, See Figs. 4A and 4C);
the second cell including second stacked source/drain regions on the at least two levels (the architecture of logic cell LC; the adjacent cell sharing a boundary with logic LC in the conventional tiled logic-cell array has the same stacked S/D architecture as the depicted logic cell LC, See for example Fig. 3);
the first cell including a first tapered vertical conductor (“A second lower via LVI2 may be provided on a bottom surface of the pad part PDP included in the second active contact AC2.”, See Par [0091]; “A second lower via LVI2 coupled to the first power line POR1 may be formed below the pad part PDP of the second active contact AC2.”, See Par [0141]; lower via LV12 formed from a backside of the device; an anisotropic backside etch inherently produces a tapered cross-section that narrows in the direction of via travel, See for example, Fig. 4D); and
the second cell including a second tapered conductor having a taper opposite that of the first tapered vertical conductor to reduce cell heights of the first cell and the second cell (“a first upper via UVI1 may be provided on a top surface of the pad part PDP included in the first active contact AC1. The first upper via UVI1 may vertically extend to the fourth wiring line MI4 from the top surface of the pad part PDP included in the first active contact AC1.”, See Par [0095]; “First and second upper vias UVI1 and UVI2 may be formed to connect the first and second active contacts AC1 and AC2 to the first metal layer M1…”, See Par [0143]; upper via UVI1 formed from a frontside of the device; an anisotropic frontside etch inherently produces a tapered cross-section having a taper opposite that of the backside-formed LV12. Furthermore, “Because a semiconductor device according to the present inventive concepts has a three-dimensional cell structure as discussed with reference to FIG. 2, the semiconductor device according to the present inventive concepts may have a relatively small cell height HE2, compared to the two-dimensional cell structure of FIG. 1.”, See Par [0100]).
Kim does not expressly disclose two cells arranged adjacent to each other.
Kim depicts a single logic cell LC with cell boundaries CB1 and CB2.
However, logic-cell layouts at the scale contemplated by Kim are inherently tiled, with cells arranged along the direction of their boundaries such that each cell shares a boundary with neighboring cell. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to arrange two of Kim’s logic cells LC adjacent to each other along the cell-boundary direction, because such tiling is the conventional manner of arranging logic cells in scaled IC design, and because Kim’s express disclosure of cell boundaries CB1 and CB2 in Par [0075] expresses tiled cell arrangement. Also, the tapered vertical conductor structures (LVI2 and UVI1) of Kim Fig. 4D are inherently present in each tiled cell. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007)
In regards to claim 2, Kim discloses (see, for example, Figs. 3 and 4) that wherein the first cell includes an I-shape having the first stacked source/drain regions on the at least two levels having a substantially same width (“Each of the first and second active regions AR1 and AR2 may have a first width W1 in the first direction D1.”, See Par [0029]; “he second source/drain patterns SD2 may correspondingly and vertically overlap the first source/drain patterns SD1.”, See Par [0045]; SD1 And SD2 grown from channel patterns CH1 and CH2 having the same width W1, producing stacked S/D regions of substantially the same width and forming the claimed I-shape configuration, See Figs. 2, 4A, and 4C).
In regards to claim 3, Kim discloses a series-chained backside-to-frontside via path (“Through vias TVI may be provided between the power delivery network PDN below the substrate 100 and the first and second power lines POR1 and POR2 on above the substrate 100. The through via TVI may have a pillar shape that extends in the third direction D3 while penetrating the substrate 100.”, See Par [0082]; “A second lower via LVI2 may be provided on a bottom surface of the pad part PDP included in the second active contact AC2.”, Par [0091]; through-via TVI in series with lower via LVI2 and connecting to upper via UVI2 via the active contact AC2, See Fig. 4D,).
Kim does not expressly disclose that the first tapered vertical conductor “includes an extended backside via that extends from a backside of the semiconductor device to a frontside of the semiconductor device” as a single continuous via.
However, it would have been obvious to a person of ordinary skill in the art at the effective filing date to consolidate Kim’s series-chained TVI/LVI2 path into a single continuous extended backside via traversing from the backside ILD to the frontside ILD, in order to reduce process steps, eliminate interface resistance between segmented vias, and reduce the cell footprint required for via landing pads. Such consolidation would have been a routine engineering optimization yielding predictable results. See KSR, 550 U.S. at 416, 82 USPQ2d at 1395.
In regards to claim 4, Kim discloses (See, for example, Figs. 3 and 4) that further comprising a backside contact connected to one of the first stacked source/drain regions and the first tapered vertical conductor at a backside of the semiconductor device (“A second lower via LVI2 may be provided on a bottom surface of the pad part PDP included in the second active contact AC2.”, See Par [0091]; “A power delivery network PDN may be provided on a bottom surface of the substrate 100.”, See Par [0080]; “Through vias TVI may be provided between the power delivery network PDN below the substrate 100 and the first and second power lines POR1 and POR2 on above the substrate 100.”, See Par [0082]; lower via LVI2 in series with through via TVI extending to power delivery network PDN at the backside of substrate 100) .
In regards to claim 7, Kim discloses (See, for example, Figs. 3 and 4) that wherein the first tapered vertical conductor passes through a shallow trench isolation (STI) region (“The first and second power lines POR1 and POR2 may be buried in the device isolation layer ST.”, See Par [0078]; “The trench TR may be filled with a device isolation layer ST. The device isolation layer ST may include a silicon oxide layer.”, See Par [0036]; lower via LVI2, in series with through via TVI, passes through device isolation layer ST containing power line POR1 to which LVI2 connects, See Fig. 4D).
In regards to claim 8, Kim discloses a dielectric collar disposed about the backside via ( “A dielectric spacer SPC may be provided on an outer sidewall of the through via TVI. The dielectric spacer SPC may insulate the through via TVI from the substrate 100.”, See Par [0082]; and dielectric spacer SPC surrounding through via TVI, See Kim Fig. 4D).
It would have been obvious to a person of ordinary skill in the art at the effective filing date to extend Kim’s dielectric spacer SPC along the entire length of the consolidated extended backside via, in order to provide continuous dielectric isolation between the backside via and adjacent gate structures across the full traversal of the via, with the predictable benefit of preventing shorting in scaled cell layouts.
In regards to claim 9, Kim discloses (See, for example, Figs. 3 and 4) that wherein the cell heights of the first cell and the second cell are each within two pitches of M1 metal lines (“The first to fourth wiring lines MI1 to MI4 may be arranged at a second pitch along the first direction D1. For example, the second pitch between the first to fourth wiring lines MI1 to MI4 may be less than the first pitch between the gate electrodes GE.”, See Par [0087]; wiring lines MI1-MI4 of first metal layer M1 arranged across the cell height HE2, See for example, Fig. 4D).
Kim does not expressly disclose that the cell heights are each within two pitches of M1 metal lines; Kim’s Fig. 4D depicts four M1 wiring lines MI1-MI4 within cell height HE2.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to reduce the number of M1 wiring lines within the cell height, including to within two M1 pitches, in order to further scale the cell size in accordance with the goal expressly identified by Kim in Par [0100]: “Because a semiconductor device according to the present inventive concepts has a three-dimensional cell structure as discussed with reference to FIG. 2, the semiconductor device according to the present inventive concepts may have a relatively small cell height HE2.” Finally, cell height reduction is a routine engineering scaling choice with predictable results. See KSR, 550 U.S. at 416, 82 USPQ2d at 1395.
Claims 5-6 and 10-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Kim in view of Hong et al. (US 2023/0411353 A1, hereinafter “Hong”).
In regards to claim 5, Kim as modified above fails to explicitly teach that the second cell includes an L-shape having the second stacked source/drain regions on the at least two levels having different widths.
Hong while disclosing a 3D stacked field effect transistors teaches (See, for example, Figs. 5 and 6) a stacked field-effect transistor structure in which the second cell includes an L-shape having the second stacked source/drain regions on the at least two levels having different widths (See claim 12; “the second S/D region 204 may be greatly expanded through, for example, increasing an amount of epitaxial growth to form the base region of the BJT, such that the second S/D region 204 with which the fourth S/D region 208 is merged may have a larger volume and larger surface area than that of the fourth S/D region 208.” See Par [0036]; “As shown in FIG. 5, the fourth S/D region 508 may be extended laterally (or longitudinally) such that at least a portion of the fourth S/D region 508 is not overlapping with the second S/D region 504. That is, the fourth S/D region 508 may include a surface having a non-overlapping section 516 distinct from a portion of the surface of the fourth S/D region 508 that is overlapping with a surface of the second S/D region 504.” See Par [0045]; and second S/D region 504 (top tier) and fourth S/D region 508 (bottom tier) have different widths, forming an L-shape with the wider bottom S/D region extending laterally past the narrower top S/D region, See Figs. 5 and 6).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the second cell of Kim’s adjacent-cell layout to incorporate the widened bottom S/D region and corresponding offset frontside contact taught by Hong, because doing so provides a larger landing area for an offset frontside contact bypassing the upper-tier S/D region
In regards to claim 6, Kim as modified above discloses (See, for example, Fig. 5, Hong) that the second tapered conductor contacts a wider second stacked source/drain region (“the SFET 500 may be connected to a back-end-of-line (BEOL) structure through a contact 518, which may be an MOL structure extending from the BEOL structure to contact the non-overlapping section 516 of the surface of the fourth S/D region 508. This non-overlapping section 516 allows for easy connection to the contact 518 extending in a direction that is the same as the direction in which the contacts 512 and 514 extend.” See Par [0045]; contact 518 landing on the laterally extended non-overlapping section 516 of wider bottom S/D region 508, See Fig. 5).
In regards to claim 10, Kim discloses (See, for example, Figs. 3 and 4) a semiconductor device, comprising:
a first cell adjacent to a second cell (See Pars [0075], [0077]);
the first cell including a first tapered vertical conductor that traverses two stacked source/drain regions in the first cell (“A first upper via UVI1 may be provided on a top surface of the pad part PDP included in the first active contact AC1. The first upper via UVI1 may vertically extend to the fourth wiring line MI4 from the top surface of the pad part PDP included in the first active contact AC1.” See Par [0095]; “the pad parts PDP of the first and second active contacts AC1 and AC2 may overlap each other, and the first and second active contacts AC1 and AC2 may be vertically connected to each other through an upper via that penetrates the pad parts PDP of the first and second active contacts AC1 and AC2. Therefore, the second source/drain pattern SD2 at a top tier may be electrically connected to the first source/drain pattern SD1 at a bottom tier.” See Par [0097]; upper via UVI1 vertically traversing the pad parts of AC1 and AC2 — which are in electrical contact with both S/D regions SD1 and SD2 — to reach wiring line MI4, See for example, Fig. 4D); and
the second tapered vertical conductor being adjacent to the first tapered vertical conductor, the second tapered vertical conductor having a taper opposite that of the first tapered vertical conductor to reduce cell heights of the first cell and the second cell (See, Pars [0091], [0095], [0100]; lower via LVI2 (in series with through via TVI) formed from backside of the device, and upper via UVI1 formed from the front side of the device).
Hong discloses (See, for example, Fig. 5) the second cell including a second tapered vertical conductor that traverses a first stacked source/drain region in the second cell and connects to a second stacked source/drain region in the second cell ( “the SFET 500 may be connected to a back-end-of-line (BEOL) structure through a contact 518, which may be an MOL structure extending from the BEOL structure to contact the non-overlapping section 516 of the surface of the fourth S/D region 508.” See Par [0045]; contact 518 traversing past second S/D region 504 (top tier) and connecting to non-overlapping section 516 of fourth S/D region 508 (bottom tier); the contact 518 has a frontside-etched negative taper, opposite to the backside-etched taper of Kim’s first tapered vertical conductor, See Hong’s Fig. 5);
Furthermore, the first tapered vertical conductor in the first cell is formed from the backside (See LVI2/TVI chain, Kim) and exhibits a positive taper widening toward the frontside, while the second tapered vertical conductor in the second cell is formed from the frontside (contact 518 landing on non-overlapping section 516, Hong) and exhibits a negative taper narrowing toward the backside, the two tapers thus being opposite.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the second cell of Kim’s adjacent-cell layout to incorporate the widened bottom S/D region and corresponding offset frontside contact taught by Hong, because doing so provides a larger landing area for an offset frontside contact bypassing the upper-tier S/D region
In regards to claim 11, Kim as modified above discloses (See, for example, Figs. 3 and 4) that the first cell includes an I-shape having the two stacked source/drain regions in the first cell with a substantially same width (See, Par [0029]).
In regards to claim 12, Kim discloses a series-chained backside-to-frontside via path (“Through vias TVI may be provided between the power delivery network PDN below the substrate 100 and the first and second power lines POR1 and POR2 on above the substrate 100. The through via TVI may have a pillar shape that extends in the third direction D3 while penetrating the substrate 100.”, See Par [0082]; “A second lower via LVI2 may be provided on a bottom surface of the pad part PDP included in the second active contact AC2.”, Par [0091]; through-via TVI in series with lower via LVI2 and connecting to upper via UVI2 via the active contact AC2, See Fig. 4D,).
Kim does not expressly disclose that the first tapered vertical conductor “includes an extended backside via that extends from a backside of the semiconductor device to a frontside of the semiconductor device” as a single continuous via.
However, it would have been obvious to a person of ordinary skill in the art at the effective filing date to consolidate Kim’s series-chained TVI/LVI2 path into a single continuous extended backside via traversing from the backside ILD to the frontside ILD, in order to reduce process steps, eliminate interface resistance between segmented vias, and reduce the cell footprint required for via landing pads. Such consolidation would have been a routine engineering optimization yielding predictable results. See KSR, 550 U.S. at 416, 82 USPQ2d at 1395.
In regards to claim 13, Kim discloses (See, for example, Figs. 3 and 4) that further comprising a backside contact connected to one of the first stacked source/drain regions and the first tapered vertical conductor at a backside of the semiconductor device (“A second lower via LVI2 may be provided on a bottom surface of the pad part PDP included in the second active contact AC2.”, See Par [0091]; “A power delivery network PDN may be provided on a bottom surface of the substrate 100.”, See Par [0080]; “Through vias TVI may be provided between the power delivery network PDN below the substrate 100 and the first and second power lines POR1 and POR2 on above the substrate 100.”, See Par [0082]; lower via LVI2 in series with through via TVI extending to power delivery network PDN at the backside of substrate 100) .
In regards to claim 14, Kim as modified above discloses (See, for example, Figs. 5, Hong) that the second cell includes an L-shape having the first stacked source/drain region in the second cell with a width that is narrower than the second stacked source/drain region in the second cell (Par [0045] regarding the differential width S/D regions).
In regards to claim 15, Kim as modified above discloses (See, for example, Fig. 5, Hong) that the second tapered conductor contacts a wider second stacked source/drain region (“the SFET 500 may be connected to a back-end-of-line (BEOL) structure through a contact 518, which may be an MOL structure extending from the BEOL structure to contact the non-
overlapping section 516 of the surface of the fourth S/D region 508. This non-overlapping section 516 allows for easy connection to the contact 518 extending in a direction that is the same as the direction in which the contacts 512 and 514 extend.” See Par [0045]; contact 518 landing on the laterally extended non-overlapping section 516 of wider bottom S/D region 508, See Fig. 5).
In regards to claim 16, Kim discloses (See, for example, Figs. 3 and 4) that wherein the first tapered vertical conductor passes through a shallow trench isolation (STI) region (“The first and second power lines POR1 and POR2 may be buried in the device isolation layer ST.”, See Par [0078]; “The trench TR may be filled with a device isolation layer ST. The device isolation layer ST may include a silicon oxide layer.”, See Par [0036]; lower via LVI2, in series with through via TVI, passes through device isolation layer ST containing power line POR1 to which LVI2 connects, See Fig. 4D).
In regards to claim 17, Kim discloses a dielectric collar disposed about the backside via ( “A dielectric spacer SPC may be provided on an outer sidewall of the through via TVI. The dielectric spacer SPC may insulate the through via TVI from the substrate 100.”, See Par [0082]; and dielectric spacer SPC surrounding through via TVI, See Kim Fig. 4D).
It would have been obvious to a person of ordinary skill in the art at the effective filing date to extend Kim’s dielectric spacer SPC along the entire length of the consolidated extended backside via, in order to provide continuous dielectric isolation between the backside via and adjacent gate structures across the full traversal of the via, with the predictable benefit of preventing shorting in scaled cell layouts.
In regards to claim 18, Kim discloses (See, for example, Figs. 3 and 4) that wherein the cell heights of the first cell and the second cell are each within two pitches of M1 metal lines (“The first to fourth wiring lines MI1 to MI4 may be arranged at a second pitch along the first direction D1. For example, the second pitch between the first to fourth wiring lines MI1 to MI4 may be less than the first pitch between the gate electrodes GE.”, See Par [0087]; wiring lines MI1-MI4 of first metal layer M1 arranged across the cell height HE2, See for example, Fig. 4D).
Kim does not expressly disclose that the cell heights are each within two pitches of M1 metal lines; Kim’s Fig. 4D depicts four M1 wiring lines MI1-MI4 within cell height HE2.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to reduce the number of M1 wiring lines within the cell height, including to within two M1 pitches, in order to further scale the cell size in accordance with the goal expressly identified by Kim: “Because a semiconductor device according to the present inventive concepts has a three-dimensional cell structure as discussed with reference to FIG. 2, the semiconductor device according to the present inventive concepts may have a relatively small cell height HE2.” in Par [0100]. Finally, cell height reduction is a routine engineering scaling choice with predictable results. See KSR, 550 U.S. at 416, 82 USPQ2d at 1395.
In regards to claim 19, Kim discloses (See, for example, Figs. 3 and 4) a semiconductor device, comprising:
a first cell including first stacked source/drain regions having a substantially same width on at least two levels (“Each of the first and second active regions AR1 and AR2 may have a first width W1 in the first direction D1.” See Par [0029]; SD1 and SD2 grown from CH1/CH2 having common width W1, producing substantially same-width stacked S/D regions, See Kim Figs. 2, 4A);
an extended backside via that extends from a backside of the semiconductor device to a frontside of the semiconductor device (“Through vias TVI may be provided between the power delivery network PDN below the substrate 100 and the first and second power lines POR1 and POR2 on above the substrate 100. The through via TVI may have a pillar shape that extends in the third direction D3 while penetrating the substrate 100.” See Par [0082]; “A second lower via LVI2 may be provided on a bottom surface of the pad part PDP included in the second active contact AC2.” See Par [0091]; See also Fig. 4D); and
a backside contact connected to one of the first stacked source/drain regions and the extended backside via at a backside of the semiconductor device (“The second lower via LVI2 may electrically connect the first power line POR1 to the second active contact AC2.” See [0091]; lower via LVI2 connecting AC2 — itself in electrical contact with second source/drain pattern SD2 — to power line POR1 at the backside, with the consolidated extended backside via terminating at this backside contact, See Fig. 4D).
Kim is silent about a second cell adjacent to the first cell including second stacked source/drain regions on the at least two levels having different widths; and a second tapered vertical conductor in the second cell having a taper opposite that of the extended backside via to reduce cell heights of the first cell and the second cell which are each within two pitches of M1 metal lines
Hong discloses (See, for example, Figs. 5 and 6) a second cell adjacent to the first cell including second stacked source/drain regions on the at least two levels having different widths ( See claim 12; “As shown in FIG. 5, the fourth S/D region 508 may be extended laterally (or longitudinally) such that at least a portion of the fourth S/D region 508 is not overlapping with the second S/D region 504. That is, the fourth S/D region 508 may include a surface having a non-overlapping section 516 distinct from a portion of the surface of the fourth S/D region 508 that is overlapping with a surface of the second S/D region 504.” See Par [0045]);
a second tapered vertical conductor in the second cell having a taper opposite that of the extended backside via to reduce cell heights of the first cell and the second cell which are each within two pitches of M1 metal lines ( “the SFET 500 may be connected to a back-end-of-line (BEOL) structure through a contact 518, which may be an MOL structure extending from the BEOL structure to contact the non-overlapping section 516 of the surface of the fourth S/D region 508.” See Par [0045]; contact 518 formed from the frontside with negative taper opposite the positive backside taper of the extended backside via.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim’s adjacent-cell layout to incorporate Hong’s differential width bottom S/D region with offset frontside contact because this non-overlapping section allows for easy connection to the contact extending in a direction that is the same as the direction in which the contacts extend.
In regards to claim 20, Kim as modified above discloses (See, for example, Figs. 3 and 4) that the extended backside via passes through a shallow trench isolation (STI) region (“The first and second power lines POR1 and POR2 may be buried in the device isolation layer ST.” See Par [0078]; through-via TVI passing through device isolation layer ST containing power lines POR1/POR2).
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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