DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 04/11/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 11-12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2021/0068261 A1) in view of Kim (JP 2012019192).
Pertaining to claim 1, Cho et al. discloses A printed circuit board (100a, see fig. 3), comprising: a plurality of insulating layers (111a – 111c and 121a – 121c, see fig. 3) having a through-portion (see fig. 3); a plurality of wiring layers (112a-112c, see fig. 3) respectively disposed on or in the plurality of insulating layers (111a – 111c and 121a – 121c, see fig. 3); a plurality of via layers (113a-113c, see fig. 3) respectively penetrating through at least a portion of at least one of the plurality of insulating layers (111a– 111c) and 121a – 121c) and respectively connected to at least one of the plurality of wiring layers (113a-113c); an electronic component (150, see fig. 3) at least partially disposed in the through-portion (see fig. 3), and embedded (see paragraph [0073-0074], lines 11-12) in at least one of the plurality of insulating layers (111a– 111c); and
But, Cho et al. does not explicitly teach an insulating film disposed in the plurality of insulating layers, and covering at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through-portion.
However, Kim teaches an insulating film (20, see fig. 3h) disposed in the plurality of insulating layers (30, see fig. 3h), and covering at least a portion of a side surface of the electronic component (11, see fig. 3h) and at least a portion of a wall surface of the through-portion (see fig. 3h).
Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide an insulating film disposed in the plurality of insulating layers, and covering at least a portion of a side surface of the electronic component and at least a portion of a wall surface of the through-portion in the device of Cho et al. based on the teachings of Kim in order to provide the module allows the molding layer to be freely formed and the electronic components to have the electrode parts placed on same level regardless of sizes of the electronic components and locations, so that the circuit patterns can be easily formed, thus enhancing manufacturing of the module.
Pertaining to claim 2, Cho et al. as modified by Kim further discloses, wherein the insulating film (20 of Kim) covers at least the portion of the side surface of the electronic component (11 of Kim) and at least the portion of the wall surface of the through-portion (see fig. 3h), with a substantially constant thickness (see paragraph 0014] of Kim).
Pertaining to claim 3, Cho et al. as modified by Kim further discloses, wherein the insulating film includes an oxide film having a thickness of less than 100 nm (see paragraph [0014] of Kim).
Pertaining to claim 4, Cho et al. discloses all claimed limitations except, wherein the oxide film includes at least one of Al2O3, TiO2, ZnO, and SiO2.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to wherein the oxide film includes at least one of Al2O3, TiO2, ZnO, and SiO2, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for intended use for the purpose of prevents delamination during manufacturing and operation. In re Leshin, 125 USPQ 416.
Pertaining to claim 5, Cho et al. as modified by Kim further discloses, wherein the electronic component (11 of Kim) has a front surface on which a pad (11a and 12a of Kim) is disposed, and a back surface opposite thereto, and the insulating film (20 of Kim) further covers at least a portion of the front surface of the electronic component (11, see fig. 2 of Kim).
Pertaining to claim 6, Cho et al. as modified by Kim further discloses, wherein the insulating film (20 of Kim) further covers at least a portion of the back surface of the electronic component (11 of Kim).
Pertaining to claim 7, Cho et al. as modified by Kim further discloses, wherein the insulating film (20 of Kim) further covers at least a portion of at least one of the plurality of wiring layers (12a of Kim).
Pertaining to claim 8, Cho et al. as modified by Kim further discloses, wherein the insulating film (20 of Kim) is in contact with at least a portion of at least one of the plurality of via layers (see paragraph [0035] of Kim).
Pertaining to claim 9, Cho et al. discloses, wherein the plurality of insulating layers (111a – 111c and 121a – 121c) includes a first insulating layer (111a) having the through-portion (see fig. 3), a second insulating layer (111b) covering at least a portion of each of the first insulating layer (111a) and the electronic component (150) and disposed in at least a portion of the through-portion (see fig. 3), and a third insulating layer (111c, see fig. 4) disposed on a lower surface of the second insulating layer (111b), the plurality of wiring layers (112a-112c include first (112a) and second wiring layers (112b) respectively disposed on an upper surface and a lower surface of the first insulating layer (111a), a third wiring layer (112c) disposed on an upper surface of the second insulating layer (111b), and a fourth wiring layer (122d, see fig. 4) disposed on a lower surface of the third insulating layer (111c), the plurality of via layers (113a-113c) includes a first via layer (113a) penetrating through at least a portion of the first insulating layer (111a), a second via layer (113b) penetrating through at least a portion of the second insulating layer (111b), and a third via layer (113c) penetrating through at least a portion of the third insulating layer (111c), and the through-portion includes a through-cavity (where component embedded) penetrating through the first insulating layer (111a).
Pertaining to claim 11, Cho et al. discloses, wherein the electronic component (150) is disposed so that the front surface faces upwardly, the wall surface of the through-cavity (wherein the component disposed or embedded), an upper surface and a side surface of the first wiring layer (112a), a side surfaces of the second wiring layer (112b), and a front surface and a side surface of the electronic component (150), and the second insulating layer (111b) covers at least a portion of the insulating layer (111).
But, Cho et al. does not explicitly teach the insulating film covers at least a portion of each of the upper surface and the lower surface of the first insulating layer.
However, Kim teaches an insulating film (20, see fig. 3h) covers at least a portion of each of the upper surface and the lower surface of the insulating layer (30, see fig. 3h).
Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide the insulating film covers at least a portion of each of the upper surface and the lower surface of the first insulating layer in the device of Cho et al. based on the teachings of Kim in order to provide comprehensive, double-sided protection and enhance overall performance in several key areas, particularly in electronic or multilayered systems.
Pertaining to claim 12, Cho et al. discloses, wherein the plurality of insulating layers (111a – 111c and 121a – 121c) include a first insulating layer (111a), a plurality of second insulating layers (111b) disposed on an upper surface of the first insulating layer (111a) and having the through-portion (see fig. 3), and a plurality of third insulating layers (111c) disposed on a lower surface of the first insulating layer (111a), the plurality of wiring layers (112a-112c) include first (112a) and second wiring layers (112b) respectively disposed on the upper surface and the lower surface of the first insulating layer (111a), a plurality of third wiring layers (112c) respectively disposed on the plurality of second insulating layers (111b), and a plurality of fourth wiring layers (122d) respectively disposed on the plurality of third insulating layers (111c), the plurality of via layers (113a-113c) include a first via layer (113a) penetrating through at least a portion of the first insulating layer (111a), a plurality of second via layers (113b) penetrating through at least a portion of each of the plurality of second insulating layers (111b), and a plurality of third via layers (113c) penetrating through at least a portion of each of the plurality of third insulating layers (111c), and the through-portion includes a blind cavity (where the component 150 embedded) penetrating through at least one of the plurality of second insulating layers (111b).
Pertaining to claim 15, Cho et al. discloses all claimed limitations except, wherein the insulating film is thinner than each of the plurality of insulating layers and each of the plurality of wiring layers, and includes a material different from the plurality of insulating layers.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to wherein the insulating film is thinner than each of the plurality of insulating layers and each of the plurality of wiring layers, and includes a material different from the plurality of insulating layers, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for intended use for the purpose of enabling device miniaturization, improving thermal management and efficiency, and enhancing overall performance and reliability. . In re Leshin, 125 USPQ 416.
Pertaining to claim 16, Cho et al. discloses A printed circuit board (100a), comprising: a plurality of insulating layers (111a – 111c and 121a – 121c); a plurality of wiring layers (112a-112c) respectively disposed on or in the plurality of insulating layers (111a – 111c and 121a – 121c); a plurality of via layers (113a-113c) respectively penetrating through at least a portion of at least one of the plurality of insulating layers (111a – 111c and 121a – 121c) and respectively connected to at least one of the plurality of wiring layers (112a-112c); an electronic component (150) disposed in the plurality of insulating layers (111a – 111c and 121a – 121c).
But, an insulating film disposed in the plurality of insulating layers and covering at least a portion of at least one portion of the plurality of wiring layers and at least a portion of the electronic component.
However, Kim teaches an insulating film (20) disposed in the plurality of insulating layers (30) and covering at least a portion of at least one portion of the plurality of wiring layers (11a) and at least a portion of the electronic component (11).
Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide the insulating film covers at least a portion of each of the upper surface and the lower surface of the first insulating layer in the device of Cho et al. based on the teachings of Kim in order to provide comprehensive, double-sided protection and enhance overall performance in several key areas, particularly in electronic or multilayered systems.
Pertaining to claim 17, Cho et al. as modified by Kim further discloses, wherein the insulating film (20 of Kim) is disposed between at least one of the plurality of insulating layers (30 of Kim) and at least one of the plurality of wiring layers (11a of Kim), and between at least one of the plurality of insulating layers (30 of Kim) and the electronic component (11 of Kim), with a substantially constant thickness (see paragraph [0014] of Kim).
Pertaining to claim 18, Cho et al. discloses all claimed limitations except, wherein the insulating film includes an alumina film.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to provide wherein the insulating film includes an alumina film, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for intended use for the purpose of superior thermal management capabilities, excellent electrical insulation, and high durability in demanding environments. In re Leshin, 125 USPQ 416.
Pertaining to claim 19, Cho et al. discloses all claimed limitations except, wherein the alumina film has a thickness of less than 100 nm.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to make wherein the alumina film has a thickness of less than 100 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Pertaining to claim 20, Cho et al. discloses all claimed limitations except, wherein the insulating film is thinner than each of the plurality of insulating layers and each of the plurality of wiring layers, and includes a material different from the plurality of insulating layers.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to provide wherein the insulating film is thinner than each of the plurality of insulating layers and each of the plurality of wiring layers, and includes a material different from the plurality of insulating layers, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of a different material is to achieve superior electrical performance, especially in high-frequency applications, and enable miniaturization of the circuit board. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
Claims 10 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: regarding claim 10, the specific limitations of “ the second insulating film covers at least a portion of each of the lower surface of the second insulating layer and a lower surface of the second wiring layer, the second insulating layer covers at least a portion of the first insulating film, and the third insulating layer covers at least a portion of the second insulating film," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record.
Referring to claim 13, the specific limitations of "the third insulating film covers at least a portion of each of a lower surface of at least one of the plurality of third insulating layers, and a lower surface and a side surface of at least one of the plurality of fourth wiring layers, at least one other of the plurality of second insulating layers covers at least a portion of the first insulating film, and at least one other of the plurality of third insulating layers covers at least a portion of the third insulating film," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Claim 14 depend from claim 13 and is therefore allowed for at the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (Wu US-20200275552-A1) and Maeda (US-20140202740-A1).
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/ANDARGIE M AYCHILLHUM/Primary Examiner, Art Unit 2848