DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 11, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 10-12, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US2017/0125360 (called Lee(1) hereinafter) in view of Minami et al. US2017/0256504 (called Minami hereinafter).
Regarding independent claim 1, Lee(1) teaches a memory device (Fig. 11; para [0041]) comprising:
a memory cell array (Fig. 11; para [0041]);
a first pad (Fig. 11; para [0058]; input end node ENI) configured to receive a command from an external device (Fig. 11; control logic 410);
a second pad configured to exchange data with the external device (Fig. 11; para [0058]; output end node ENO);
a test logic (Fig. 10) configured to generate a test pulse signal (Fig. 11; S200) based on a test command received through the first pad (Fig. 11; control logic 410 provides the commands to the crack detector CDET 500); and
wherein a crack occurring in the third pad is detected based on a delay of a delay pulse signal changed when the test pulse signal passes through the crack detection structure (para [0089]; a phase difference or a delay time of the test input signal when compared with the test output signal may be used to indicate a crack).
Lee(1) fails to teach a third pad; a crack detection structure arranged below the third pad and configured to include lines connected in series from the test logic to the second pad.
Minami teaches a third pad (Fig. 7; pads 9); a crack detection structure (Figs. 6 and 7; crack detection unit 8 and lines with pads 9) arranged below the third pad (Fig. 6) and configured to include lines connected in series from the test logic to the second pad (Fig. 7; lines through pads 9 are in series).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) with the crack detection of pads as described by Minami for the purpose of improving the reliability of the semiconductor device by improving the detection of a defective product and suppress degradation of product yield due to excessively strict specifications (para [0055]).
Regarding claim 7, Lee(1) and Minami teach the memory device of claim 1, Lee(1) further teaches wherein it is determined that a crack exists in the third pad when the delay of the delay pulse signal is greater than a reference value (para [0089]).
Regarding claim 10, Lee(1) and Minami teach the memory device of claim 1, Lee(1) further teaches further comprising: an input/output circuit (Fig. 11; combination of control logic 410, bank control logic 430, I/O gating 490, and data I/O buffer 495) configured to perform input or output of data stored in the memory cell array (Fig. 11; memory cell array 480), wherein the input/output circuit is configured to output the delay pulse signal through the second pad (Fig. 11; control logic 410 provides the commands to and from the crack detector CDET 500).
Regarding independent claim 11, Lee(1) teaches a method (Abstract) of detecting cracks in a memory device (Fig. 11; para [0041]), the method comprising:
transmitting a test command from a test device (Fig. 11; control logic 410 provides the commands to the crack detector CDET 500) to the memory device;
generating a test pulse signal based on the test command (Fig. 11; S200);
transmitting the test pulse signal through a crack detection structure (Fig. 11; crack detection structure CDST 500);
outputting a delay pulse signal (para [0089]) which has passed through the crack detection structure to the test device through a data pad of the memory device (Figs. 11 and 23; para [0041-0042, 0158]); and
comparing the test pulse signal and the delay pulse signal to determine whether the test target pad contains a crack based on a delay of the delay pulse signal (para [0089]; a phase difference or a delay time of the test input signal when compared with the test output signal may be used to indicate a crack).
Lee(1) fails to teach transmitting the test pulse signal through a crack detection structure arranged below a test target pad.
Minami teaches transmitting the test pulse signal through a crack detection structure arranged below a test target pad (Figs. 6 and 7; crack detection unit 8 is under pads 9).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) with the crack detection of pads as described by Minami for the purpose of improving the reliability of the semiconductor device by improving the detection of a defective product and suppress degradation of product yield due to excessively strict specifications (para [0055]).
Regarding claim 12, Lee(1) and Minami teach the method of claim 11, Lee(1) further teaches wherein the determining whether the test target pad contains a crack includes determining that the crack exists in the test target pad when the delay of the delay pulse signal is greater than a reference value (para [0089]).
Regarding independent claim 17, Lee(1) teaches a memory device (Fig. 11; para [0041]) comprising:
test target pads (Fig. 11; para [0058]; input end node ENI and output end node ENO);
a test logic (Fig. 10) configured to generate a test pulse signal (Fig. 11; S200) based on a test command received from an external device (Fig. 11; control logic 410 provides the commands to the crack detector CDET 500); and
a crack detection circuit (Fig. 11; CDET 500) configured to determine whether cracks occur in the test target pads based on a delay of a delay pulse signal changed when the test pulse signal passes through the crack detection structure (para [0089]; a phase difference or a delay time of the test input signal when compared with the test output signal may be used to indicate a crack).
Lee(1) fails to teach a crack detection structure arranged below the test target pads and including lines connected in series across the test target pads.
Minami teaches a crack detection structure (Figs. 6 and 7; crack detection unit 8 and lines with pads 9) arranged below the test target pads (Figs. 6 and 7; pads 9) and including lines connected in series across the test target pads (Fig. 7; lines are in series across the pads 9); and a crack detection circuit (Figs. 6 and 7; crack detector 100) configured to determine whether cracks occur in the test target pads based on a delay of a delay pulse signal changed when the test pulse signal passes through the crack detection structure.
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) with the crack detection of pads as described by Minami for the purpose of improving the reliability of the semiconductor device by improving the detection of a defective product and suppress degradation of product yield due to excessively strict specifications (para [0055]).
Regarding claim 18, Lee(1) and Minami teach the memory device of claim 17, Minami further teaches further comprising: a first metal layer on which the test target pads are arranged (Fig. 6; electrode pad metal layer 22); a first insulating layer stacked below the first metal layer (Fig. 6; insulating layer between 22 and 18-2); a second metal layer stacked below the first insulating layer (Fig. 6; interconnect layer 18-2); a second insulating layer stacked below the second metal layer (Fig. 6; insulating layer between 18-2 and 18-1); and a third metal layer stacked below the second insulating layer (Fig. 6; interconnect layer 18-1).
Claim(s) 2-6, 15-16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee(1), in view of Minami and further in view of Sabouret et al. US11018096 (called Sabouret hereinafter and applicant disclosed art).
Regarding claim 2, Lee(1) and Minami teach the memory device of claim 1, Minami further teaches wherein the crack detection structure comprises: first line portions crossing the third pad in a first direction (Fig. 7; lines in pads 9 that are in the north-south direction); second line portions connecting the first line portions (Fig. 7; lines in pads 9 that are in the east-west direction).
Lee(1) and Minami fail to teach a via connecting one of the first line portions and one of the second line portions.
Sabouret teaches a via connecting one of the first line portions and one of the second line portions (Fig. 6A and 6B; vias VRa and VRb used to connect conductors for crack sensing).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing lines in different layers as described by Sabouret for the purpose of improving the detection of cracks by sensing fine cracks that does not initially impact the electric conduction of the metal tracks (Column 2 lines 63-67).
Regarding claim 3, Lee(1), Minami and Sabouret teach the memory device of claim 2, the combination of Lee(1), Minami and Sabouret further teaches wherein the third pad is on a first metal layer (Minami; Figs. 6 and 7; electrode pad metal layer 22), wherein the first line portions are on a second metal layer stacked below the first metal layer (Sabouret; Fig. 6B; Rb), wherein the second line portions are on a third metal layer stacked below the second metal layer (Sabouret; Fig. 6B; Ra), wherein the first metal layer and the second metal layer are separated by a first insulating layer (Sabouret; Fig. 6B; insulating layer between Rc and Rb), and wherein the via is configured to penetrate a second insulating layer stacked between the second metal layer and the third metal layer (Fig. 6B; via VRa goes through insulating layer between Rb and Ra) and connect one of the first line portions and one of the second line portions (Fig. 6B; Rb and Ra).
Regarding claim 4, Lee(1), Minami and Sabouret teach the memory device of claim 2, Minami further teaches wherein a length of each of the first line portions is configured to be longer than a length of each of the second line portions (Fig. 7; the lines in pad 9 in the north-south direction are longer than the lines in the east-west direction).
Regarding claim 5, Lee(1), Minami and Sabouret teach the memory device of claim 2, Minami further teaches wherein the first line portions are arranged in parallel and spaced apart at specified intervals (Fig. 7; the lines in pad in the north-south direction are parallel and spaced apart in equal intervals from each other).
Regarding claim 6, Lee(1) and Minami teach the memory device of claim 1, Minami further teaches wherein the crack detection structure comprises: a first line portion curved in a plurality of directions to overlap the third pad vertically (Figs. 6 and 7; lines in pad 9).
Lee(1) and Minami fail to teach a second line portion connected to one end of the first line portion through a first via; and a third line portion connected to another end of the first line portion through a second via.
Sabouret teaches a second line portion connected to one end of the first line portion through a first via (Fig. 6B; Rc connected to Rb through the left via VRb); and a third line portion connected to another end of the first line portion through a second via (Fig. 6B; Rc connected to Rb through the right via VRb).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing lines in different layers as described by Sabouret for the purpose of improving the detection of cracks by sensing fine cracks that does not initially impact the electric conduction of the metal tracks (Column 2 lines 63-67).
Regarding claim 15, Lee(1) and Minami teach the method of claim 11, Minami further teaches wherein the crack detection structure comprises: first line portions crossing the test pad in a first direction (Fig. 7; lines in pads 9 that are in the north-south direction); second line portions configured to connect between the first line portions (Fig. 7; lines in pads 9 that are in the east-west direction).
Lee(1) and Minami fail to teach a via configured to connect one of the first line portions and one of the second line portions.
Sabouret teaches a via configured to connect one of the first line portions and one of the second line portions (Fig. 6A and 6B; vias VRa and VRb used to connect conductors for crack sensing).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing lines in different layers as described by Sabouret for the purpose of improving the detection of cracks by sensing fine cracks that does not initially impact the electric conduction of the metal tracks (Column 2 lines 63-67).
Regarding claim 16, Lee(1) and Minami teach the method of claim 11, Minami further teaches wherein the crack detection structure comprises: a first line portion curved in a plurality of directions to overlap the test target pad vertically (Figs. 6 and 7; lines in pad 9).
Lee(1) and Minami fail to teach a second line portion connected to one end of the first line portion through a first via; and a third line portion connected to another end of the first line portion through a second via.
Sabouret teaches a second line portion connected to one end of the first line portion through a first via (Fig. 6B; Rc connected to Rb through the left via VRb); and a third line portion connected to another end of the first line portion through a second via (Fig. 6B; Rc connected to Rb through the right via VRb).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing lines in different layers as described by Sabouret for the purpose of improving the detection of cracks by sensing fine cracks that does not initially impact the electric conduction of the metal tracks (Column 2 lines 63-67).
Regarding claim 19, Lee(1) and Minami teach the memory device of claim 18, but fails to teach wherein the crack detection structure comprises: first line portions formed on the second metal layer and overlapped by a specified ratio or more of areas of each of the test target pads; and second line portions arranged on the third metal layer and connected to the first line portions through vias penetrating the second insulating layer such that the first line portions are connected in series.
Sabouret teaches wherein the crack detection structure comprises: first line portions formed on the second metal layer (Fig. 6B; second part Rb) and overlapped by a specified ratio or more of areas of each of the test target pads (Figs. 5, 6A and 6B; second part Rb overlaps the target area of the structure ST by a ratio); and second line portions arranged on the third metal layer (Figs. 6A and 6B; first parts Ra) and connected to the first line portions through vias penetrating the second insulating layer such that the first line portions are connected in series (Figs. 6A and 6B; vias VRa connect Ra and Rb together in series).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing lines in different layers as described by Sabouret for the purpose of improving the detection of cracks by sensing fine cracks that does not initially impact the electric conduction of the metal tracks (Column 2 lines 63-67).
Claim(s) 8 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee(1), in view of Minami and further in view of Lee et al. US20170103929 (called Lee(2) hereinafter).
Regarding claim 8, Lee(1) and Minami teach the memory device of claim 1, but fail to teach wherein it is determined that a crack exists in the third pad when an edge slope of the delay pulse signal is less than a reference value.
Lee(2) teaches wherein it is determined that a crack exists in the third pad when an edge slope of the delay pulse signal is less than a reference value (Fig. 5; para [0122-0123]; the DQ0(FAIL) signal has a differing slope than the CKE signal).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing output signals as described by Lee(2) for the purpose of determining a particular location of the crack in the substrate and gate pattern (para [0123]).
Regarding claim 13, Lee(1) and Minami teach the method of claim 11, but fails to teach wherein the determining whether the test target pad contains a crack includes determining that the crack exists in the test target pad when an edge slope of the delay pulse signal is less than a reference value.
Lee(2) teaches wherein the determining whether the test target pad contains a crack includes determining that the crack exists in the test target pad when an edge slope of the delay pulse signal is less than a reference value (Fig. 5; para [0122-0123]; the DQ0(FAIL) signal has a differing slope than the CKE signal).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing output signals as described by Lee(2) for the purpose of determining a particular location of the crack in the substrate and gate pattern (para [0123]).
Regarding claim 14, Lee(1) and Minami teach the method of claim 11, but fail to teach wherein the determining whether the test target pad contains a crack includes determining that the crack exists in the test target pad when a delay value of the delay pulse signal deviates from a normal distribution.
Lee(2) teaches wherein the determining whether the test target pad contains a crack includes determining that the crack exists in the test target pad when a delay value of the delay pulse signal deviates from a normal distribution (Fig. 5; para [0122-0123]; the DQ0(FAIL) signal has a differing signal than the CKE signal, thus leading to a differing normal distribution between the CKE and DQ0(FAIL) signal).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Lee(1) and Minami with the crack sensing output signals as described by Lee(2) for the purpose of determining a particular location of the crack in the substrate and gate pattern (para [0123]).
Allowable Subject Matter
Claims 9 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the prior arts of record taken alone or in combination fail to teach or suggest:
“further comprising: a command decoder configured to output a test enable signal based on the test command, wherein the test logic is configured to generate the test pulse signal by combining the test enable signal and a crack detection signal received through the first pad and the crack detection signal having a specified delay.”
Regarding claim 20, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein the first line portions are configured to be arranged across at least two of the test target pads in a direction in which the test target pads are arranged, and the first line portions arranged in parallel and spaced apart at a specified interval.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. discloses “Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die” (see US2020/0091021)
Periyannan et al. discloses “Die crack detection” (see US2020/0103462)
Kwon et al. discloses “Crack detection chip and crack detection method using the same” (see US2019/0265291)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID B FREDERIKSEN whose telephone number is (571)272-8152. The examiner can normally be reached M-F 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID B FREDERIKSEN/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858