DETAILED ACTION
This action is responsive to the amendments filed May 26, 2026. Prior to entry, claims 1-20 were pending. Claims 1, 2, 4, 9, 11-13, 18, and 19 are amended. Claims 3, and 20 are cancelled. Thus, upon entry, claims 1-2, and 4-19 are pending. Claims 1, 11, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 4-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1 and 18, those claims define the terms "first memory cells", "second memory cells", "third memory cells", and "fourth memory cells" by reference to a specific high-end one-to-one mapping. The claims that depend from claim 1 (2 and 4 for example) and the claims that depend from claim 18 (i.e., 19) refer to those same terms with apparently different definitions.
Regarding independent claim 11, the claim also defines the terms "first memory cells", "second memory cells", "third memory cells", "fourth memory cells", and "fifth memory cells" but assigns them different meanings than that of claims 1 and 8. The claims that depend from claim 11 (i.e.; 12) again refer to those same terms with apparently different definitions.
Because the identical labels are given inconsistent definitions in different independent and dependent claims, and they do not unambiguously clarify which definition is to be uniformly applied, a person of ordinary skill in the art cannot determine the metes and bounds of the claims with reasonable certainty.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hara et al. (US 20210158867; “Hara” – of record) in view of Kondo (US 2020019078).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation, and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Regarding independent claims 1, and 18, notwithstanding the rejection for indefiniteness above, Hara discloses a memory device comprising:
a plurality of memory cells (Fig. 2, NAND memory cell array 23) including first memory cells, second memory cells, third memory cells, and fourth memory cells;
a peripheral circuit configured to perform a program operation including storing data in the plurality of memory cells (Fig. 2, Control Unit 22);
and a program operation control circuit configured to, during the program operation,
control the peripheral circuit to perform a foggy program operation including increasing first threshold voltages of the plurality of memory cells to second threshold voltages corresponding to any one state among an erase state and first to sixth foggy program states (Fig. 26 where it illustrates a foggy (also known as “coarse” first programming operation with erase state and first to sixth foggy program states),
and perform a fine program operation including increasing the second threshold voltages of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states (Fig. 26 where it illustrates a fine programming step with 15 final program states).
It is noted that the foggy program feature is apparently directed to Fig. 6 of the instant application. While the specification describes advantages of an intermediate programming step in general, no rationale is given for explicitly dividing the range into six states, nor are any explicit voltage values indicated for those six states, nor are any explicit voltage values indicated for those six states. The total defined range of threshold voltage values for the foggy program step appears arbitrary other than the visual indication of sequentially increasing from the erase state.
There is a known design need to reduce program interference between proximate memory cells in a multi-level cell array. Using an initial course (foggy) programming step followed by a fine programming step is a well-known method of mitigating such interference. Hara discloses foggy-fine programming with a reduced number of intermediate threshold regions, but is silent with respect to maintaining a one-to-one correspondence between intermediate foggy states and the highest fine program states.
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However, Kondo teaches wherein the program operation control circuit is configured to control the peripheral circuit such that, during the fine program operation, first memory cells corresponding to the third [fourth from the end] foggy program state have third threshold voltages corresponding to the twelfth fine program state, second memory cells corresponding to the fourth [third from the end] foggy program state have fourth threshold voltages corresponding to the thirteenth fine program state, third memory cells corresponding to the fifth [second from the end] foggy program state have fifth threshold voltages corresponding to the fourteenth fine program state, and fourth memory cells corresponding to the sixth [at the end, or last] foggy program state have sixth threshold voltages corresponding to the fifteenth fine program state (See Examiner's markup above and para. 70; "Memory cells MT to be finally programmed up to the S1 state during the fine programming are programmed up to the FS1 state during the preceding foggy programming. Memory cells MT to be finally programmed up to the S2 state during the fine programming are programmed up to the FS2 state during the preceding foggy programming. Similarly, memory cells MT to be finally programmed up to the S3 to S15 states during the fine programming are programmed respectively to the FS3 to FS15 states during the preceding foggy programming." It is noted that Kondo shows the final four threshold distributions (S12-S15) after the fine programming pass. The one-to-one correspondence is therefore illustrated for every state, including the four highest states. Hara teaches the use of a reduced number of intermediate states (six or seven) in a foggy-fine scheme. When the reduced intermediate count framework of Hara is combined with the one-to-one high end mapping principle of Kondo, the resulting intermediate states include distinct high-end intermediate states that correspond one-to-one to the highest final states (12th – 15th program states). The particular labeling of those high-end states as the "third", "fourth", "fifth", and "sixth" foggy program states is a predictable consequence of numbering a reduced set of intermediate states that preserves the separation of the four highest final states. No new functionality is required beyond what the combination already teaches.).
Hara and Kondo are from the same field of endeavor as applicant' s invention directed to foggy-fine programming methods of multi-level cell memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the reduced intermediate state programming foggy-fine framework of Hara by adopting the one-to-one high-end mapping as taught by Kondo. Both references address the same recognized problem of neighbor word line interference in multi-level cell programming (see Hara, para. 227 and Kondo, para. 30). Combining the teachings would have yielded the predictable result of preserving separation of the highest threshold distributions during the intermediate stage, thereby further reducing the effects of neighbor word line interference on those high-Vth states while retaining the programming speed benefits already provided by Hara's reduced intermediate count.
Regarding claim 2. Hara and Kondo combined disclose the limitations of claim 1.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
during the fine program operation, the first memory cells having threshold voltages corresponding to each of the erase state and the first and second foggy program states have threshold voltages corresponding to each of the erase state and the first to eleventh fine program states (Fig. 26 where it illustrates the first and second foggy program state transitions to the lower end and middle of the fine program states).
Regarding claim 4, Hara and Kondo combined disclose the limitations of claim 1.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
during the fine program operation, third memory cells having threshold voltages corresponding to the second foggy program state have a threshold voltage corresponding to each of the eighth to eleventh fine program states (Fig. 26 where it illustrates the second foggy program state transitions to the middle of the range of fine program states).
Regarding claim 5, Hara and Kondo combined discloses the limitations of claim 1.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the foggy program operation by using foggy verify voltages corresponding to the first to sixth foggy program states (Fig. 26 where it illustrates the six verify voltages (Vr4’-Vr14’) corresponding to the six foggy program states).
Regarding claim 6, Hara and Kondo disclose the limitations of claim 5.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the fine program operation when foggy verify operations using the foggy verify voltages pass (Fig. 26 where it illustrates the foggy verify voltages Vr4’-Vr14’. See also para. 246; “After each program voltage pulse, reading called verifying is performed to confirm whether or not the memory cell moves beyond the threshold boundary level”).
Regarding claim 7, Hara and Kondo combined disclose the limitations of claim 1.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the foggy program operation on memory cells connected to a word line adjacent to a word line connected to the plurality of memory cells before the fine program operation on the plurality of memory cells is performed (para. 247; “the control unit 22 may continuously execute the first stage program and the second stage program for one word line WLi, but in order to reduce the influence of interference between adjacent memory cells, the program may be executed in a discontinuous order across a plurality of word lines WLi.”)
Regarding claim 8, Hara and Kondo combined disclose the limitations of claim 1.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the fine program operation by using a plurality of logical page data received from an external device (Fig. 1: 4 Host external to the memory device. See also para. 136; “The memory controller 2 controls the writing of data to the nonvolatile memory 3 in accordance with a write command from the host 4”).
Regarding claim 9, Hara and Kondo combined disclose the limitations of claim 8.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to read first and second logical page data among the plurality of logical page data from the plurality of memory cells during the fine program operation (para 226; “The program can be made in two stages of the first stage program that combines the Lower page and the Middle page”. It is noted that Hara’s lower page and middle page correspond to the LSB and CSB of Fig. 8 and para. 98 of the instant application and for which this feature appears directed).
Regarding claim 10, Hara and Kondo combined disclose the limitations of claim 9.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the fine program operation by the first and second logical page data and third and fourth logical page data received from the external device among the plurality of logical page data (para. 147; “Each bit written to each memory cell corresponds to a different page. In this embodiment, the four pages of one memory cell group MG are referred to as a Lower page (first page), a Middle page (second page), an Upper page (third page), and a Top page (fourth page)”).
Regarding independent claim 11, Hara discloses a memory device comprising:
a plurality of memory cells (Fig. 2, NAND memory cell array 23) including first memory cells, second memory cells, third memory cells, fourth memory cells, and fifth memory cells;
a peripheral circuit configured to perform a program operation including increasing threshold voltages of the plurality of memory cells (Fig. 2, Control Unit 22);
and a program operation control circuit configured to, during the program operation,
control the peripheral circuit to perform a foggy program operation including increasing the threshold voltages of the plurality of memory cells to threshold voltages corresponding to each of first to sixth foggy program states (Fig. 26 where it illustrates a foggy (also known as “coarse” first programming operation),
and perform a fine program operation including increasing threshold voltages of first memory cells corresponding to the first foggy program state or the second foggy program state to threshold voltages corresponding to each of fourth to seventh fine program states or each of eighth to eleventh fine program states among an erase state and first to fifteenth fine program states (Fig. 26 where it illustrates a fine programming steps with 15 final program states of which the first and second foggy program state transitions to the lower end of fine program states),
It is noted that the foggy program feature is apparently directed to Fig. 6 of the instant application. While the specification describes advantages of an intermediate programming step in general, no rationale is given for explicitly dividing the range into six states, nor are any explicit voltage values indicated for those six states, nor are any explicit voltage values indicated for those six states. The total defined range of threshold voltage values for the foggy program step appears arbitrary other than the visual indication of sequentially increasing from the erase state.
There is a known design need to reduce program interference between proximate memory cells in a multi-level cell array. Using an initial course (foggy) programming step followed by a fine programming step is a well-known method of mitigating such interference. Hara discloses foggy-fine programming with a reduced number of intermediate threshold regions, but is silent with respect to maintaining a one-to-one correspondence between intermediate foggy states and the highest fine program states.
However, Kondo teaches and increasing threshold voltages of second memory cells corresponding to the third foggy program state to threshold voltages corresponding to the twelfth [fourth from the end] fine program state, and increasing threshold voltages of third memory cells corresponding to the fourth foggy program state to threshold voltages corresponding to the thirteenth [third from the end] fine program state, and increasing threshold voltages of fourth memory cells corresponding to the fifth foggy program state to threshold voltages corresponding to the fourteenth [second to the end] fine program state, and increasing threshold voltages of fifth memory cells corresponding to the sixth foggy program state to threshold voltages corresponding to the fifteenth [at the end – or last] fine program state (See Examiner's markup above and para. 70; "Memory cells MT to be finally programmed up to the S1 state during the fine programming are programmed up to the FS1 state during the preceding foggy programming. Memory cells MT to be finally programmed up to the S2 state during the fine programming are programmed up to the FS2 state during the preceding foggy programming. Similarly, memory cells MT to be finally programmed up to the S3 to S15 states during the fine programming are programmed respectively to the FS3 to FS15 states during the preceding foggy programming." It is noted that Kondo shows the final four threshold distributions (S12-S15) after the fine programming pass. The one-to-one correspondence is therefore illustrated for every state, including the four highest states. Hara teaches the use of a reduced number of intermediate states (six or seven) in a foggy-fine scheme. When the reduced intermediate count framework of Hara is combined with the one-to-one high end mapping principle of Kondo, the resulting intermediate states include distinct high-end intermediate states that correspond one-to-one to the highest final states (12th – 15th program states). The particular labeling of those high-end states as the "third", "fourth", "fifth", and "sixth" foggy program states is a predictable consequence of numbering a reduced set of intermediate states that preserves the separation of the four highest final states. No new functionality is required beyond what the combination already teaches.).
Hara and Kondo are from the same field of endeavor as applicant' s invention directed to foggy-fine programming methods of multi-level cell memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the reduced intermediate state programming foggy-fine framework of Hara by adopting the one-to-one high-end mapping as taught by Kondo. Both references address the same recognized problem of neighbor word line interference in multi-level cell programming (see Hara, para. 227 and Kondo, para. 30). Combining the teachings would have yielded the predictable result of preserving separation of the highest threshold distributions during the intermediate stage, thereby further reducing the effects of neighbor word line interference on those high-Vth states while retaining the programming speed benefits already provided by Hara's reduced intermediate count.
Regarding claim 12, Hara and Kondo combined disclose the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
during the fine program operation, threshold voltages of third memory cells corresponding to the erase state increases to threshold voltages corresponding to each of the erase state and the first to third fine program states (Fig. 26 where it illustrates the erase state foggy program transitioning to the first to third fine program states).
Regarding claim 13, Hara and Kondo combined disclose the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit includes a word line control circuit configured to control the peripheral circuit to apply foggy verify voltages corresponding to the first to sixth foggy program states to a word line connected to the plurality of memory cells during the foggy program operation (Fig. 2: 34 voltage supply unit within the 22 control unit. See also para. 160; “The voltage supply unit 34 generates various internal voltages supplied to the word lines”. It is noted that as Hara’s memory device discloses the utilization of a foggy-fine programming scheme, the word line voltages applied would necessarily result in the first to sixth foggy program states.).
Regarding claim 14, Hara as supported by Tabrizi discloses the limitations of claim 13.
As applied, Hara further discloses wherein the word line control circuit controls the peripheral circuit to
apply a fine program voltage to the word line after foggy verify operations using the foggy verify voltages pass (Fig. 26 where it illustrates the foggy verify voltages Vr4’-Vr14’. See also para. 246; “After each program voltage pulse, reading called verifying is performed to confirm whether or not the memory cell moves beyond the threshold boundary level”).
Regarding claim 15, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit to
perform the fine program operation on memory cells connected to a word line adjacent to a word line connected to the plurality of memory cells before the foggy program operation on the plurality of memory cells is performed (para. 247; “the control unit 22 may continuously execute the first stage program and the second stage program for one word line WLi, but in order to reduce the influence of interference between adjacent memory cells, the program may be executed in a discontinuous order across a plurality of word lines WLi.”).
Regarding claim 16, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit to
perform the foggy program operation by using first to fourth logical page data received from an external device (para. 147; “Each bit written to each memory cell corresponds to a different page. In this embodiment, the four pages of one memory cell group MG are referred to as a Lower page (first page), a Middle page (second page), an Upper page (third page), and a Top page (fourth page)”).
Regarding claim 17, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit to
perform the fine program operation by using first and second logical page data read from the plurality of memory cells and third and fourth logical page data received from the external device (para 226; “The program can be made in two stages of the first stage program that combines the Lower page and the Middle page”. It is noted that Hara’s lower page and middle page correspond to the LSB and CSB of Fig. 8 and para. 98 of the instant application and for which this feature appears directed)).
Regarding claim 19, Hara as supported by Tabrizi discloses the limitations of claim 18.
As applied, Hara further discloses wherein,
in the performing of the fine program operation, a threshold voltage of first memory cells, which corresponds to each of the erase state and the first and second foggy program states, among the plurality of memory cells increases to a threshold voltage corresponding to each of the erase state and the first to eleventh fine program states (Fig. 26 where it illustrates the erase state and first and second foggy program state transitions to the lower and middle end of fine program states).
Hara’s mapping of foggy states to fine states in Fig. 26 differs from that of the instant application. The correspondence of “fine programming states” data values to threshold voltage level (e.g. “data coding”) of a quadruple level cell (QLC) technology is a well-known design choice (see Tabrizi, Fig. 1 and pg. 371, col 2, sect III) used to improve data reliability, speed and endurance by alleviating the technical challenges (e.g. error correction, logical to physical mapping, requirement for background refreshing, and proximity disturbance) of very narrow margins for error between the 16 discrete threshold voltage states. Therefore, transitioning from a given course (foggy) programming state to a given fine programming state is merely a function of choosing between a finite number of data-coding schemes with predictable outcomes which would be obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention. Doing so would yield a predictable result with regard to the routine design constraint being optimized. See also Figs. 17-25 of Hara for additional examples of differing data-coding schemes and how they map coarse to fine.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant contends on pg. 13 of Remarks that the obviousness rejection of independent claims 1, 11 and 18 is improper because the previously cited references fail, alone or in combination, to teach or suggest all the features of the claims. Applicant amended the claims to expressly require a one-to-one correspondence in which the final four intermediate (foggy) programmed states map to the final four fine states. Applicant argues that Hara's Fig. 26 illustrates only a many-to-one mapping (multiple fine states collapsed into a single intermediate foggy state) and is therefore deficient. Additionally, applicant further argues that the claimed one-to-one allocation reduces fluctuation of the high Vth fine-program-state distributions caused by word-line interference, an advantage allegedly not recognized or achieved by Hara.
The amendments have been entered. The rejections under 35 U.S.C. § 103 have been withdrawn and new grounds of rejection are set forth above. The new grounds are necessitated by the amendments.
The precise one-to-one intermediate-to-final mapping that applicant identifies as missing from Hara is taught by Kondo, and is taught for the same recognized purpose – reduction of neighbor word line interference – that applicant asserts as the advantage of the claimed arrangement. When Hara's reduced intermediate count foggy-fine framework is combined with Kondo's one-to-one high-end mapping, the resulting combination produces intermediate states that include distinct high-end intermediate states corresponding one-to-one to the twelfth through fifteenth fine program states. The particular labeling of those high-end intermediate states as the "third" through "sixth" foggy program states is a predictable consequence of numbering a reduced set of intermediate states that preserves separation of the four highest final states.
Applicant's assertion that the claimed one-to-one high-end mapping yields a reduction in high-Vth distribution fluctuation is therefore not an unexpected result. It is the predictable outcome of adopting the one-to-one mapping that Kondo already teaches for the purpose of suppressing neighbor word line interference. The combination of Hara and Kondo renders the amended independent claims, and the claims that depend therefrom, obvious under 35 U.S.C. § 103.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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