DETAILED ACTION
This action is responsive to the application filed April 11, 2024. Claims 1-20 are pending. Claims 1, 11, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on April 11, 2024. This IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hara et al. (US 20210158867; “Hara”) as supported by Tabrizi et al. (“Improving NAND flash read performance through learning”; “Tabrizi”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation, and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
PNG
media_image1.png
741
947
media_image1.png
Greyscale
Regarding independent claims 1, and 18, Hara discloses a memory device comprising:
a plurality of memory cells (Fig. 2, NAND memory cell array 23);
a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells (Fig. 2, Control Unit 22);
and a program operation control circuit configured to, in the program operation,
control the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states (Fig. 26 where it illustrates a foggy (also known as “coarse” first programming operation with erase state and first to sixth foggy program states),
and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states (Fig. 26 where it illustrates a fine programming step with 15 final program states).
It is noted that the foggy program feature is apparently directed to Fig. 6 of the instant application. While applicant’s specification details the advantages of an intermediate programming step in general, no rationale is given for explicitly dividing the range into six states, nor are any explicit voltage values indicated for those six states. In fact, the total defined range of threshold voltage values for the foggy program step appears to be arbitrary other than the visual indication of sequentially increasing from the erase state.
There is a known design need to reduce program interference between proximate floating gate memory cells in an array. Using an initial coarse programming step is an identified and predictable method well known in the art as a program interference mitigation method. Choosing from a finite number and values of intermediate threshold voltage states across an arbitrary range would be a routine design choice obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention. Doing so would yield a predictable result of speeding up the overall program operation by reducing the need for multiple rewriting efforts of neighboring cells.
Regarding claim 2. Hara as supported by Tabrizi discloses the limitations of claim 1.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
in the fine program operation, first memory cells having a threshold voltage corresponding to each of the erase state and the first and second foggy program states among the plurality of memory cells have a threshold voltage corresponding to each of the erase state and the first to eleventh fine program states (Fig. 26 where it illustrates the first and second foggy program state transitions to the lower end and middle of the fine program states).
Hara’s mapping of foggy states to fine states in Fig. 26 differs from that of the instant application. The correspondence of “fine programming states” data values to threshold voltage level (e.g. “data coding”) of a quadruple level cell (QLC) technology is a well-known design choice (see Tabrizi, Fig. 1 and pg. 371, col 2, sect III) used to improve data reliability, speed and endurance by alleviating the technical challenges (e.g. error correction, logical to physical mapping, requirement for background refreshing, and proximity disturbance) of very narrow margins for error between the 16 discrete threshold voltage states. Therefore, transitioning from a given coarse (foggy) programming state to a given fine programming state is merely a function of choosing between a finite number of data-coding schemes with predictable outcomes which would be obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention. Doing so would yield a predictable result with regard to the routine design constraint being optimized. See also Figs. 17-25 of Hara for additional examples of differing data-coding schemes and how they map coarse to fine.
Regarding claim 3, Hara as supported by Tabrizi discloses the limitations of claim 1.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
in the fine program operation, second memory cells having a threshold voltage corresponding to each of the third to sixth foggy program states among the plurality of memory cells have a threshold voltage corresponding to each of the twelfth to fifteenth fine program states, respectively (Fig. 26 where it illustrates the third to sixth foggy program state transitions to the higher end of fine program states).
Id., and for the same reasons.
Regarding claim 4, Hara as supported by Tabrizi discloses the limitations of claim 1.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
in the fine program operation, third memory cells having a threshold voltage corresponding to the second foggy program state among the plurality of memory cells have a threshold voltage corresponding to each of the eighth to eleventh fine program states (Fig. 26 where it illustrates the second foggy program state transitions to the middle of the range of fine program states).
Id., and for the same reasons.
Regarding claim 5, Hara as supported by Tabrizi discloses the limitations of claim 1.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the foggy program operation by using foggy verify voltages corresponding to the first to sixth foggy program states (Fig. 26 where it illustrates the six verify voltages (Vr4’-Vr14’) corresponding to the six foggy program states).
Regarding claim 6, Hara as supported by Tabrizi discloses the limitations of claim 5.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the fine program operation when foggy verify operations using the foggy verify voltages pass (Fig. 26 where it illustrates the foggy verify voltages Vr4’-Vr14’. See also para. 246; “After each program voltage pulse, reading called verifying is performed to confirm whether or not the memory cell moves beyond the threshold boundary level”).
Regarding claim 7, Hara as supported by Tabrizi discloses the limitations of claim 1.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the foggy program operation on memory cells connected to a word line adjacent to a word line connected to the plurality of memory cells before the fine program operation on the plurality of memory cells is performed (para. 247; “the control unit 22 may continuously execute the first stage program and the second stage program for one word line WLi, but in order to reduce the influence of interference between adjacent memory cells, the program may be executed in a discontinuous order across a plurality of word lines WLi.”)
Regarding claim 8, Hara as supported by Tabrizi discloses the limitations of claim 1.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the fine program operation by using a plurality of logical page data received from an external device (Fig. 1: 4 Host external to the memory device. See also para. 136; “The memory controller 2 controls the writing of data to the nonvolatile memory 3 in accordance with a write command from the host 4”).
Regarding claim 9, Hara as supported by Tabrizi discloses the limitations of claim 8.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to read first and second logical page data among the plurality of logical page data from the plurality of memory cells in the fine program operation (para 226; “The program can be made in two stages of the first stage program that combines the Lower page and the Middle page”. It is noted that Hara’s lower page and middle page correspond to the LSB and CSB of Fig. 8 and para. 98 of the instant application and for which this feature appears directed).
Regarding claim 10, Hara as supported by Tabrizi discloses the limitations of claim 9.
As applied, Hara further discloses wherein
the program operation control circuit controls the peripheral circuit to perform the fine program operation by the first and second logical page data and third and fourth logical page data received from the external device among the plurality of logical page data (para. 147; “Each bit written to each memory cell corresponds to a different page. In this embodiment, the four pages of one memory cell group MG are referred to as a Lower page (first page), a Middle page (second page), an Upper page (third page), and a Top page (fourth page)”).
Regarding independent claim 11, Hara discloses a memory device comprising:
a plurality of memory cells (Fig. 2, NAND memory cell array 23);
a peripheral circuit configured to perform a program operation of increasing a threshold voltage of the plurality of memory cells (Fig. 2, Control Unit 22);
and a program operation control circuit configured to, in the program operation,
control the peripheral circuit to perform a foggy program operation of increasing the threshold voltage of the plurality of memory cells to a threshold voltage corresponding to each of first to sixth foggy program states (Fig. 26 where it illustrates a foggy (also known as “coarse” first programming operation),
and perform a fine program operation of increasing a threshold voltage of first memory cells corresponding to the first foggy program state or the second foggy program state among the plurality of memory cells to a threshold voltage corresponding to each of fourth to seventh fine program states or each of eighth to eleventh fine program states among an erase state and first to fifteenth fine program states (Fig. 26 where it illustrates a fine programming steps with 15 final program states of which the first and second foggy program state transitions to the lower end of fine program states),
and increasing a threshold voltage of second memory cells corresponding to each of the third to sixth foggy program states among the plurality of memory cells to a threshold voltage corresponding to each of the twelfth to fifteenth fine program states (Fig. 26 where it illustrates the third to sixth foggy programming states transitioning to the top of the fine programming states).
Hara’s mapping of foggy states to fine states in Fig. 26 differs from that of the instant application. It is noted that the claimed foggy-fine program feature is apparently directed to Fig. 6 of the instant application. While applicant’s specification details the advantages of an intermediate programming step in general, no rationale is given for explicitly dividing the range into six states, nor are any explicit voltage values indicated for those six states. In fact, the total defined range of threshold voltage values for the foggy program step appears to be arbitrary other than the visual indication of sequentially increasing from the erase state.
Additionally, the correspondence of “fine programming states” data values to threshold voltage level (e.g. “data coding”) of a quadruple level cell (QLC) technology is a well-known design choice (see Tabrizi, Fig. 1 and pg. 371, col 2, sect III) used to improve data reliability, speed and endurance by alleviating the technical challenges (e.g. error correction, logical to physical mapping, requirement for background refreshing, and proximity disturbance) of very narrow margins for error between the 16 discrete threshold voltage states. Therefore, transitioning from a given coarse (foggy) programming state to a given fine programming state is merely a function of choosing between a finite number of data-coding schemes with predictable outcomes which would be obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention. Doing so would yield a predictable result with regard to the routine design constraint being optimized. See also Figs. 17-25 of Hara for additional examples of differing data-coding schemes and how they map coarse to fine.
Regarding claim 12, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit such that,
in the fine program operation, a threshold voltage of third memory cells corresponding to the erase state among the plurality of memory cells increases to a threshold voltage corresponding to each of the erase state and the first to third fine program states (Fig. 26 where it illustrates the erase state foggy program transitioning to the first to third fine program states).
Regarding claim 13, Hara as supported by Tabrizi discloses the limitations of claim 11.
wherein the program operation control circuit includes ()
a word line control circuit configured to control the peripheral circuit to apply foggy verify voltages corresponding to the first to sixth foggy program states to a word line connected to the plurality of memory cells in the foggy program operation (Fig. 2: 34 voltage supply unit within the 22 control unit. See also para. 160; “The voltage supply unit 34 generates various internal voltages supplied to the word lines”. It is noted that as Hara’s memory device discloses the utilization of a foggy-fine programming scheme, the word line voltages applied would necessarily result in the first to sixth foggy program states.).
Regarding claim 14, Hara as supported by Tabrizi discloses the limitations of claim 13.
As applied, Hara further discloses wherein the word line control circuit controls the peripheral circuit to
apply a fine program voltage to the word line after foggy verify operations using the foggy verify voltages pass (Fig. 26 where it illustrates the foggy verify voltages Vr4’-Vr14’. See also para. 246; “After each program voltage pulse, reading called verifying is performed to confirm whether or not the memory cell moves beyond the threshold boundary level”).
Regarding claim 15, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit to
perform the fine program operation on memory cells connected to a word line adjacent to a word line connected to the plurality of memory cells before the foggy program operation on the plurality of memory cells is performed (para. 247; “the control unit 22 may continuously execute the first stage program and the second stage program for one word line WLi, but in order to reduce the influence of interference between adjacent memory cells, the program may be executed in a discontinuous order across a plurality of word lines WLi.”).
Regarding claim 16, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit to
perform the foggy program operation by using first to fourth logical page data received from an external device (para. 147; “Each bit written to each memory cell corresponds to a different page. In this embodiment, the four pages of one memory cell group MG are referred to as a Lower page (first page), a Middle page (second page), an Upper page (third page), and a Top page (fourth page)”).
Regarding claim 17, Hara as supported by Tabrizi discloses the limitations of claim 11.
As applied, Hara further discloses wherein the program operation control circuit controls the peripheral circuit to
perform the fine program operation by using first and second logical page data read from the plurality of memory cells and third and fourth logical page data received from the external device (para 226; “The program can be made in two stages of the first stage program that combines the Lower page and the Middle page”. It is noted that Hara’s lower page and middle page correspond to the LSB and CSB of Fig. 8 and para. 98 of the instant application and for which this feature appears directed)).
Regarding claim 19, Hara as supported by Tabrizi discloses the limitations of claim 18.
As applied, Hara further discloses wherein,
in the performing of the fine program operation, a threshold voltage of first memory cells, which corresponds to each of the erase state and the first and second foggy program states, among the plurality of memory cells increases to a threshold voltage corresponding to each of the erase state and the first to eleventh fine program states (Fig. 26 where it illustrates the erase state and first and second foggy program state transitions to the lower and middle end of fine program states).
Hara’s mapping of foggy states to fine states in Fig. 26 differs from that of the instant application. The correspondence of “fine programming states” data values to threshold voltage level (e.g. “data coding”) of a quadruple level cell (QLC) technology is a well-known design choice (see Tabrizi, Fig. 1 and pg. 371, col 2, sect III) used to improve data reliability, speed and endurance by alleviating the technical challenges (e.g. error correction, logical to physical mapping, requirement for background refreshing, and proximity disturbance) of very narrow margins for error between the 16 discrete threshold voltage states. Therefore, transitioning from a given coarse (foggy) programming state to a given fine programming state is merely a function of choosing between a finite number of data-coding schemes with predictable outcomes which would be obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention. Doing so would yield a predictable result with regard to the routine design constraint being optimized. See also Figs. 17-25 of Hara for additional examples of differing data-coding schemes and how they map coarse to fine.
Regarding claim 20, Hara as supported by Tabrizi discloses the limitations of claim 18.
As applied, Hara further discloses wherein,
in the performing of the fine program operation, a threshold voltage of second memory cells, which corresponds to each of the third to sixth foggy program states, among the plurality of memory cells increases to a threshold voltage corresponding to each of the twelfth to fifteenth fine program states, respectively (Fig. 26 where it illustrates the third to sixth foggy program state transitions to the higher end of fine program states).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825