Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device claims 1-14 in the reply filed on 7/6/2026 is acknowledged. The examiner notes that the Requirement for Restriction/Election (CTRS) filed 5/6/2026 contains a clear typo, listing claim 15 to be drawn both a device and method, where claim 15 is clearly a method. Therefore, because device claims were elected, claims 15-20 (drawn to a method) are a nonelected/withdrawn claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang (US 20250234504 A1).
Regarding claim 1, Wang discloses, in [0006]:
“Embodiments of the present disclosure provide a memory comprising: . . . a plurality of memory cell columns distributed in a first direction perpendicular to the substrate, each of the memory cell columns comprising a plurality of memory cells disposed and stacked along the first direction, different memory cell columns being arranged on the substrate along a second direction and a third direction to form an array; the second direction and the third direction being intersected and the formed plane being parallel to the main plane of the substrate . . .”
(a semiconductor device comprising an array structure comprising a plurality of memory cells), [0006] further states:
“. . . the memory cell comprising a transistor and a capacitor disposed in sequence along the second direction . . .“
(wherein a memory cell of the plurality of memory cells comprises a transistor and a capacitor that are stacked together along a first direction (“second direction”)), [0006] further states:
“. . . the transistor comprising a semiconductor layer and a gate, the semiconductor layer extending as a strip structure along the second direction, the strip structure having sidewalls and both ends, and the sidewall in the second direction comprising a source region, a channel region and a drain region, the source region and the drain region being adjacent to two ends of the semiconductor layer . . .”
(wherein the transistor comprises a transistor body (“channel region”), a first terminal (“drain region”), a second terminal (“source region”), and a gate structure (“gate”), the first terminal and the second terminal being on opposite ends of the transistor body along the first direction (“second direction”), [0006] further states:
“. . . the gate encircling the sidewalls of the second semiconductor layer in the channel region . . .”
Also see FIG. 1B, showing the gate 12 extending along the “second direction” (corresponding to the first direction of claim 1) and being adjacent to the transistor body 114 along the “first direction” (corresponding to the second direction in claim 1) (the gate structure extending along the first direction and being adjacent to the transistor body along a second direction perpendicular to the first direction), [0006] further states:
“. . . an electrode and a dielectric layer of the capacitor encircling the sidewall of a second semiconductor layer in the drain region. . . . “
Also see FIG. 1A, where “first electrode plate” 21 is in contact with the terminal (drain region 113) of the transistor, and there is continuous contact along the “second direction” (first direction of claim 1) (wherein the first terminal of the transistor is in contact with a first electrode of the capacitor along the first direction), the examiner also notes that, as mentioned above “the gate encircling the sidewalls” means that there is a curved or angled portion of the gate around the body portion, which means that there are portions of the end of the conductive film of the gate which are curved or angled, therefore the left side of the gate labeled 12 in FIG. 1A has a curved or angled end which is closer to the first terminal than the second terminal (and wherein the gate structure comprises a conductive film having an angled or curved end closer to the first terminal of the transistor than the second terminal of the transistor). The examiner notes that gates inherently have conductive films therein.
Regarding claim 8, Wang further teaches, in FIG. 1A, that the array structure further comprises a plurality of bit lines (300) and one of the plurality of bit lines is in contact with the second terminal of the transistor, and the adjacent bit lines are isolated by a corresponding isolating region (see region in which bit lines are spaced apart from one another).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20250234504 A1).
Regarding claim 2, as explained above, Wang teaches the limitations of claim 1, Wang further teaches, in FIG. 1B, wherein the transistor body comprises a “second semiconductor layer” (first body) 115 and a “first semiconductor layer” 114 (second body) that are in contact with each other along the “first direction) (second direction of claim 2), paragraph [0014] states “In an embodiment . . . a material for the first semiconductor layer [second body] is selected from any one or more of Group IVA semiconductor materials, for example, the material for the first semiconductor layer is single-crystal silicon,” [0015] states “In an embodiment . . . the material for the second semiconductor layer may be a metal oxide semiconductor material, the metal in the metal oxide comprising at least one of indium, zinc, tungsten, tin, titanium, zirconium, hafnium, and gallium.“ The examiner notes that IGZO (indium-gallium-zinc-oxide) semiconductors fall within this group, and have a higher electron mobility than both amorphous silicon (a group IVA material) and silicon crystal (see above). The examiner also notes that FIG. 1B shows the second body being closer to the gate 12 than the first body.
It would have been obvious to one having ordinary skill in the art at the effective filing date to choose an IGZO semiconductor material for the second body (or any other listed material for the second body that has a higher electron mobility than the materials listed for the first body). One having ordinary skill in the art is motivated to do so in order to, for example, to take advantage of the excellent and well known electrical characteristics of IGZO semiconductor channels (or other listed material combinations with high electron mobility).
Regarding claim 3, as explained above, Wang teaches that the first body is made of group IVA materials and that the second body can be made of IGZO.
It would have been obvious to one having ordinary skill in the art at the effective filing date to select amorphous silicon (a group IVA material) for the first semiconductor body, as taught by Wang. One having ordinary skill in the art is motivated to do so in order to, for example, reduce manufacturing cost and complexity, as amorphous silicon is well known to be cheaper and simpler to manufacture than, for example, crystalline silicon.
Regarding claim 4, as explained above, Wang teaches that the second semiconductor material (which is part of the transistor body) comprises IGZO.
It would have been obvious to one having ordinary skill in the art at the effective filing date to choose IGZO as a material of the transistor body, as taught by Wang. One having ordinary skill in the art is motivated to do so in order to, for example, take advantage of the excellent and well known electrical properties of IGZO transistors.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20250234504 A1) in view of Kim (US 20230035916 A1).
Regarding claim 5, as explained above, Wang teaches the limitations of claim 1, Wang further teaches, in FIG. 3A, that the array structure comprises “isolation material” (isolating region) 700 (see legend) that is between transistors of two adjacent memory cells of the plurality of memory cells, wherein the isolating region has a first end close to first terminals of the transistors and a second end close to second terminals of the transistors.
Wang does not teach that first end has a smaller size than the second end.
Kim teaches, in FIG. 7, a semiconductor device comprising two memory cells (each cell comprising “oxide semiconductor layer” (channel) “upper contact layer” (first terminal) and “lower contact layer” (second terminal), which make up a transistor, and a “second contact structure” 292 and “first contact structure” 296 which make up a capacitor). The semiconductor device further comprises “isolation insulating layer” (isolating region) that is between transistors of two adjacent memory cells of the plurality of memory cells, wherein the isolating region has a first end close to first terminals of the transistors and a second end close to second terminals of the transistors, and the first end has a smaller size than the second end.
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the device taught by Wang such that the isolating region has a first end close to first terminals of the transistors and a second end close to second terminals of the transistors, and the first end has a smaller size than the second, as taught by Kim. One having ordinary skill in the art is motivated to do so in order to, for example, allowing for more room for the capacitors, increasing the reliability of the device (as increased capacitor size would increase capacitance, allowing for improved charge retention and reducing the refresh interval).
Claim(s) 6-7, 10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20250234504 A1) in view of Ohuchi (US 20080185683 A1).
Regarding claim 6, Wang further teaches, in FIG. 1C, a “dielectric layer” (dielectric structure) 23 (also see legend of FIG. 1D and beginning of [0093]) extending along the “second direction” (first direction of claim 6) and the “first electrode plate” (first electrode) 21 is on at least one surface of the dielectric structure and wherein the dielectric structure has a first end and a second end opposite to each other along the first direction, and wherein the first end is closer to the first terminal of the transistor than the second end.
Wang does not teach that the first end has a greater size than the second end.
Ohuchi teaches, in FIG. 1, a first terminal 152 which is connected to a lower electrode” (first electrode) 171, further, “interlayer insulating film” (dielectric structure) 163 extends along a first direction (the direction that the transistor – which comprises gate electrode 114, active region 111, and “diffusion regions” 121 and 122 (source and drain regions) – and the capacitor 170 are stacked along) wherein the dielectric structure has a first end and a second end opposite to each other along the first direction, and wherein the first end is closer to the first terminal of the transistor (122) than the second end, and the first end has a greater size than the second end.
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the device taught by Wang such that the dielectric structure’s first end has a greater size than the second end, as taught by Ohuchi. One having ordinary skill in the art is motivated to do so in order to, for example, utilize less costly etching techniques to pattern the capacitor structure, as the tapered capacitor holes etched into the dielectric structure (Ohuchi, FIG. 1) can be achieved via cheaper (non-anisotropic) etching means, such as wet etching, rather than requiring more costly anisotropic etching techniques to form right angles. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 7, Wang teaches, in FIG. 1C, a second electrode 22. Wang does not teach a capacitor body.
Ohuchi further teaches, in FIG. 1, a second electrode 172 and a “capacitive film” (capacitor body) 173 between the first and second electrode, wherein the first electrode encloses the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body, and wherein the array structure comprises “insulating film[s]” (supporting structures) 163 and 161 extending along the second direction (direction perpendicular to the aforementioned first direction, in the left-to-right direction of FIG. 1) and being distributed along the first direction between the between first electrodes of two adjacent capacitors (although not directly between).
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Wang such that the capacitor comprises a capacitor body between the first and second electrode, the first electrode encloses the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body, and such that the array structure comprises supporting structures extending along the second direction and being distributed along the first direction between the first electrode and the second electrode or between first electrodes of two adjacent capacitors, as taught by Ohuchi. One having ordinary skill in the art is motivated form the capacitor body to increase the capacitance of the capacitor (by increasing the dielectric constant of the gap), to form the capacitor body and dielectric structure as above mentioned to provide support and isolation for the semiconductor layers, and to form the supporting structures to isolate various components (such as transistors, bit lines, word lines) and provide structure to the device, allowing operability.
Regarding claim 10, as explained above, Wang teaches a semiconductor device, comprising: an array structure comprising a plurality of memory cells, wherein a memory cell of the plurality of memory cells comprises a transistor and a capacitor that are stacked together along a first direction, wherein the transistor comprises a transistor body, a first terminal, a second terminal, and a gate structure, the first terminal and the second terminal being on opposite ends of the transistor body along the first direction, the gate structure extending along the first direction and being adjacent to the transistor body along a second direction perpendicular to the first direction, wherein the first terminal of the transistor is in contact with a first electrode of the capacitor along the first direction.
Furthermore, Wang teaches, in ,” [0015] states “In an embodiment . . . the material for the second semiconductor layer may be a metal oxide semiconductor material, the metal in the metal oxide comprising at least one of indium, zinc, tungsten, tin, titanium, zirconium, hafnium, and gallium.“ The examiner notes that IGZO (indium-gallium-zinc-oxide) semiconductors fall within this group. FIG. 1C, teaches that the capacitor comprises a “dielectric layer” (dielectric structure) 23 (also see legend of FIG. 1D and beginning of [0093]) extending along the “second direction” (first direction of claim 10) and the “first electrode plate” (first electrode) 21 is on at least one surface of the dielectric structure and wherein the dielectric structure has a first end and a second end opposite to each other along the first direction, and wherein the first end is closer to the first terminal of the transistor than the second end.
Wang does not teach that the first end has a greater size than the second end along the second direction.
Ohuchi teaches, in FIG. 1, a first terminal 152 which is connected to a lower electrode” (first electrode) 171, further, “interlayer insulating film” (dielectric structure) 163 extends along a first direction (the direction that the transistor – which comprises gate electrode 114, active region 111, and “diffusion regions” 121 and 122 (source and drain regions) – and the capacitor 170 are stacked along) wherein the dielectric structure has a first end and a second end opposite to each other along the first direction, and wherein the first end is closer to the first terminal of the transistor (122) than the second end, and the first end has a greater size along a second direction (which is perpendicular to the first direction, left-to-right in the figure) than the second end.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Wang such that the transistor body comprises IGZO as further taught by Wang, and such that the first end of the dielectric structure has a greater size than a second end of the dielectric structure along the second direction, as taught by Ohuchi. One having ordinary skill in the art is motivated to utilize IGZO in the transistor body because of its excellent and well known electrical properties, and is motivated to form the first end of the dielectric structure such that it is larger than the second end in order to enable cheaper etching techniques such as wet etching. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 12, Wang further teaches, in [0006] that the “. . . the gate [is] encircling the sidewalls of the second semiconductor layer in the channel region . . .” The examiner notes that this means that the gate structure has angled or curved portions along its length. FIG. 1A further shows that the gate structure has an end (which is angled or curved, see above) which is closer to the first terminal of the transistor than the second terminal of the transistor. The examiner notes that gates inherently have a conductive film.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20250234504 A1) in view of Or-Bach (US 20230329013 A1).
Regarding claim 9, as explained above, Wang teaches the limitations of claim 8. Wang does not teach that the semiconductor device comprises a second die.
Or-Bach teaches, in [0027]:
“a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the array of memory cells includes a plurality of memory control-lines, and where at least one of the plurality of memory control-lines is directly connected to at least one of the metal to metal bonding regions.”
Therefore, Or-Bach teaches a first die (“memory level”) and a second die (“first level including control circuits”) on which an array of memory cells is implemented, where the first die is bonded to the second die (“first level is bonded to the memory level”). The examiner notes that the memory array “includes a plurality of memory control-lines” (bit lines) and further bond between the dies includes “oxide to oxide bonding regions,” and further that these oxide to oxide regions cover the bit lines (at least partially, as they are disposed over/under them at the bonding region) and is in contact with the second die (the control circuit, note that even if there may be intervening layers, being in contact with the control circuit does not require direct, uninterrupted contact); “at least one of the plurality of memory control-lines is directly connected to at least one of the metal to metal bonding regions” (a bit line is connected to the control circuit through a conductive interconnection).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Wang such that there is a second semiconductor die which contains a control circuit, one of the bit lines is coupled to the control circuit, and a surface of a cover layer over the bit-lines is in contact with a surface of the control circuit, as taught Or-Bach. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that the device can function by providing a control circuit, improving thermal performance by forming the control circuit on a separate die, and decreasing manufacturing complexity by forming the cover layer in contact with the control circuit.
However, Or-Bach does not explicitly teach that the plurality of bit lines is closer to the second die than the capacitor. Applicant has not disclosed that the plurality of bit lines being closer to the second die than the capacitor provides an advantage, is used for a particular purpose, or solves a stated problem other than the well-known and unsurprising function of a bit line coupled to a second control die
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the semiconductor device of Wang and Or-Bach to form the bit line such that it is closer to the second die than to the capacitor. This is because one of ordinary skill in the art would have expected this layout to be one of several straightforward design variations of coupling a control circuit on a second die to a bit line because the necessary connection is still achieved.
Claim(s) 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20250234504 A1) in view of Ohuchi (US 20080185683 A1) in further view of Kim (US 20230035916 A1).
Regarding claim 11, as explained above, Wang and Ohuchi teach the limitations of claim 10. Wang further teaches, in FIG. 1A, an isolation region that is between transistors of two adjacent cells of the plurality of memory cells and that the isolating region has a first end close to first terminals of the transistors and a second end close to second terminals of the transistors.
Wang does not teach that the first end has a smaller size than the second end.
Kim teaches Kim teaches, in FIG. 7, a semiconductor device comprising two memory cells (each cell comprising “oxide semiconductor layer” (channel) “upper contact layer” (first terminal) and “lower contact layer” (second terminal), which make up a transistor, and a “second contact structure” 292 and “first contact structure” 296 which make up a capacitor). The semiconductor device further comprises “isolation insulating layer” (isolating region) that is between transistors of two adjacent memory cells of the plurality of memory cells, wherein the isolating region has a first end close to first terminals of the transistors and a second end close to second terminals of the transistors, and the first end has a smaller size than the second end.
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the device taught by Wang such that the isolating region has a first end close to first terminals of the transistors and a second end close to second terminals of the transistors, and the first end has a smaller size than the second, as taught by Kim. One having ordinary skill in the art is motivated to do so in order to, for example, allowing for more room for the capacitors, increasing the reliability of the device (as increased capacitor size would increase capacitance, allowing for improved charge retention and reducing the refresh interval).
Regarding claim 13, Wang further teaches, in FIG. 1C, a second electrode 22. Wang does not teach a capacitor body.
Ohuchi further, teaches, in FIG. 1, a second electrode 172 and a “capacitive film” (capacitor body) 173 between the first and second electrode, wherein the first electrode encloses the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body, and wherein the array structure comprises “insulating film[s]” (supporting structures) 163 and 161 extending along the second direction (direction perpendicular to the aforementioned first direction, in the left-to-right direction of FIG. 1) and being distributed along the first direction between the between first electrodes of two adjacent capacitors (although not directly between).
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Wang such that the capacitor comprises a capacitor body between the first and second electrode, the first electrode encloses the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body, and such that the array structure comprises supporting structures extending along the second direction and being distributed along the first direction between the first electrode and the second electrode or between first electrodes of two adjacent capacitors, as taught by Ohuchi. One having ordinary skill in the art is motivated form the capacitor body to increase the capacitance of the capacitor (by increasing the dielectric constant of the gap), to form the capacitor body and dielectric structure as above mentioned to provide support and isolation for the semiconductor layers, and to form the supporting structures to isolate various components (such as transistors, bit lines, word lines) and provide structure to the device, allowing operability.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20250234504 A1) in view of Ohuchi (US 20080185683 A1) in further view of Or-Bach (US 20230329013 A1).
Regarding claim 14, as stated above, Wang and Ohchi teach the limitations of claim 10. Wang further teaches, in FIG. 1A, that the array structure further comprises a plurality of bit lines (300) and one of the plurality of bit lines is in contact with the second terminal of the transistor, and the adjacent bit lines are isolated by a corresponding isolating region (see region in which bit lines are spaced apart from one another).
Wang does not teach a second die.
Or-Bach teaches, in [0027]:
“a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the array of memory cells includes a plurality of memory control-lines, and where at least one of the plurality of memory control-lines is directly connected to at least one of the metal to metal bonding regions.”
Therefore, Or-Bach teaches a first die (“memory level”) and a second die (“first level including control circuits”) on which an array of memory cells is implemented, where the first die is bonded to the second die (“first level is bonded to the memory level”). The examiner notes that the memory array “includes a plurality of memory control-lines” (bit lines) and further bond between the dies includes “oxide to oxide bonding regions,” and further that these oxide to oxide regions cover the bit lines (at least partially, as they are disposed over/under them at the bonding region) and is in contact with the second die (the control circuit, note that even if there may be intervening layers, being in contact with the control circuit does not require direct, uninterrupted contact); “at least one of the plurality of memory control-lines is directly connected to at least one of the metal to metal bonding regions” (a bit line is connected to the control circuit through a conductive interconnection).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Wang such that there is a second semiconductor die which contains a control circuit, one of the bit lines is coupled to the control circuit, and a surface of a cover layer over the bit-lines is in contact with a surface of the control circuit, as taught Or-Bach. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that the device can function by providing a control circuit, improving thermal performance by forming the control circuit on a separate die, and decreasing manufacturing complexity by forming the cover layer in contact with the control circuit.
However, Or-Bach does not explicitly teach that the plurality of bit lines is closer to the second die than the capacitor. Applicant has not disclosed that the plurality of bit lines being closer to the second die than the capacitor provides an advantage, is used for a particular purpose, or solves a stated problem other than the well-known and unsurprising function of a bit line coupled to a second control die
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the semiconductor device of Wang and Or-Bach to form the bit line such that it is closer to the second die than to the capacitor. This is because one of ordinary skill in the art would have expected this layout to be one of several straightforward design variations of coupling a control circuit on a second die to a bit line because the necessary connection is still achieved.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jang (US 10693015 B2) – Curved or angled gate conductive film.
H. Kim (US 20210358913 A1) – IGZO and amorphous silicon layers used in conjunction [0022].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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