DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1 and 6.
b. Pending: 1-17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu PG PUB 20230363153 (hereinafter Zhu), in view of RAJASHEKHAR PG PUB 20210202703 (hereinafter RAJASHEKHAR).
Regarding independent claim 1, Zhu teaches a NOR memory array (title of Zhu) comprising:
multiple vertical memory groups (“a vertical memory group” has been interpreted as one vertical stack under one gate stack, thus in figure 21, each WL forms a vertical stack of memory cells) arranged in n rows (WL direction) and m columns (bit line direction) on a horizontal plane, wherein one vertical memory group includes at least h vertically stacked memory transistors, where n, m, and h are natural numbers greater than 1 (figure 21 of Zhu, [0091]-[0094] of Zhu, “…a two-dimensional array of memory cells MC is shown … A plurality of such two-dimensional arrays may be arranged in a direction (for example, a direction perpendicular …so as to obtain a three-dimensional array…an extension direction of the word lines WL1 to WL3 may correspond to an extension direction of the gate stack, that is, the vertical direction with respect to the substrate…”),
wherein, the memory transistors in the one vertical memory group share a vertically extended columnar gate structure (claim 1 of Zhu, “…a gate stack that extends vertically with respect to the substrate to pass through each of the plurality of device layers…”),
part or all of the columnar gate structures of vertical memory groups in a same row are connected to a same word line (figure 21 of Zhu, [0091]-[0092]/[0088] of Zhu, “…the contact portion 1039 may be electrically connected to a word line. A gate control signal may be applied to the gate conductor layer 1027 through the word line via the contact portion 1039…”),
part or all of the memory transistors located at a same stack layer in vertical memory groups in a same column are connected to a same bit line ([0092]-[0093] of Zhu, “…eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8…”, [0088] of Zhu, “…source/drain regions … electrically connected to the bit lines via the contact portion 1041 respectively…”) and
an isolation part, for isolating active areas and bit lines of the memory transistors in the adjacent columns, is arranged between adjacent columns of the vertical memory groups (Zhu teaches isolation layers between device layers and isolation plugs, and adjacent bit line are isolated from each other, [0094] of Zhu, “…adjacent bit lines are isolated from each other...”)
However, Zhu does not explicitly teach an isolation structure arranged between adjacent vertical memory groups.
RAJASHEKHAR teaches insulating layers interlaces with source and drain layers and inter-transistor-level isolating layers located between vertical nonboring pairs (claim 9 of RAJASHEKHAR, “…insulating layers interlaced with the source layers and the drain layers of the alternating stack, wherein the insulating layers comprise: channel-level insulating layers in contact with a respective one of the semiconductor channels; and inter-transistor-level insulating layers located between vertically neighboring pairs of the channel-level insulating layers and not contacting any of the semiconductor channels…”). RAJASHEKHAR’s insulating layers are arranged between adjacent vertical memory structures, thereby isolating active areas and conductive lines between adjacent vertical memory groups.
Both Zhu and RAJASHEKHAR are directed to three-dimensional NOR-type memory architectures employing vertically stacked device layers and vertical gate structures. The substitution of known isolation techniques from RAJASHEKHAR into Zhu’s structure would have been a predictable use of prior art elements according to their established function. It would have been obvious to a person having ordinary skill in the art at the time of effective filing to incorporate RAJASHEKHAR’s insulating structure between adjacent vertical memory stacks into Zhu’s NOR memory array, in order to improve electrical isolation between adjacent memory components.
Regarding claim 2, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 1, wherein, the one vertical memory group comprises h+1 source/drain layers and h channel layers alternately stacked in a vertical direction (claim 1 of Zhu, “…a plurality of device layers stacked on a substrate, wherein each of the plurality of device layers comprises a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first source/drain region and the second source/drain region in the vertical direction…”, [0031]/[0094] of Zhu, Zhu teaches alternating source/drain regions and channel regions stacked vertically, claim 1 of RAJASHEKHAR, “…an alternating stack of source layers and drain layers located over a substrate… vertical stacks of discrete semiconductor channels…”), wherein each channel layer and two source/drain layers contacted therewith in the vertical direction construct an active area of one memory transistor (Zhu teaches that each device layer forms a memory cell defined at a position where the gate conductor layer intersects a corresponding device layer via the memory function layer, claim 1 and [0114] of Zhu, each memory cell include a channel region between source/drain regions), wherein two adjacent memory transistors in the vertical direction share a common source/drain layer ([0092] of Zhu, “…every two adjacent device layers may share the same source line connection…”) and the h+1 source/drain layers are respectively connected to h+1 metal lines that construct the respective bit lines or source lines of the h memory transistors ([0092]/[0088] of Zhu, “…For every two adjacent memory cells in the vertical direction, source/drain regions located in the middle, i.e. the source/drain region 1009.sub.1 in the first device layer 1005.sub.1 and the source/drain region 1007.sub.2 in the second device layer 1005.sub.2, or the source/drain region 1009.sub.3 in the third device layer 1005.sub.3 and the source/drain region 1007.sub.4 in the fourth device layer 1005.sub.4, may be electrically connected to a source line via the common contact portion 1041... source/drain regions located at upper and lower ends, i.e. the source/drain region 1007.sub.1 in the first device layer 1005.sub.1 and the source/drain region 1009.sub.2 in the second device layer 1005.sub.2, or the source/drain region 1007.sub.3 in the third device layer 1005.sub.3 and the source/drain region 1009.sub.4 in the fourth device layer 1005.sub.4, may be electrically connected to the bit lines via the contact portion 1041 respectively…”)
Regarding claim 3, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 2, wherein, the vertical memory groups in the same column share the h+1 source/drain layers, and contacts for respectively connecting to the h+1 metal lines that construct the respective bit lines or source lines of the h memory transistors are respectively provided at ends of the source/drain layers of each column ([0087]-[0088] of Zhu, figure 18 of Zhu, claim 1 of RAJASHEKHAR).
Regarding claim 4, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 1, wherein, at least one column of the vertical memory groups includes i sub-columns of the vertical memory groups, where i is a natural number greater than 1; wherein the columnar gate structures of at least two adjacent sub-columns of the vertical memory groups are spaced in the column direction (claim 5 of Zhu teaches a plurality of gate stacks, gate stacks arranged adjacent to one another, RAJASHEKHAR teaches in claim 1 memory openings and vertical stacks laterally separated from each other, thus adjacent vertical structures are spaced apart).
Regarding claim 5, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 4, wherein, each columnar gate structure in the i sub-columns has a same distance from each of the columnar gate structures adjacent to it in the column direction; or, each columnar gate structure in the i sub-columns has a same distance from each of the columnar gate structures adjacent to it in the row direction; or, each columnar gate structure in the i sub-columns has a same distance from each of the columnar gate structures adjacent to it in the row or column direction (Zhu teaches in [0091]/[0093] and figure 21 a 2D array of gate stacks arranged regularly in rows and columns. A regular array inherent requires uniform spacing between adjacent gate stacks in row and column directions, RAJASHEKHAR teaches memory openings vertically extending through alternating stacks, arranged periodically (see claim 1 of RAJASHEKHAR), such fabrication results in uniform spacing between adjacent vertical memory structures).
Regarding independent claim 6, the combination of Zhu and RAJASHEKHAR teaches a NOR memory array (title of Zhu) comprising:
multiple vertical memory groups (“a vertical memory group” has been interpreted as one vertical stack under one gate stack, thus in figure 21, each WL forms a vertical stack of memory cells) arranged in n rows (WL direction) and m columns (bit line direction) on a horizontal plane, wherein one vertical memory group includes at least h vertically stacked memory transistors, where n, m, and h are natural numbers greater than 1 (figure 21 of Zhu, [0091]-[0094] of Zhu, “…a two-dimensional array of memory cells MC is shown … A plurality of such two-dimensional arrays may be arranged in a direction (for example, a direction perpendicular …so as to obtain a three-dimensional array…an extension direction of the word lines WL1 to WL3 may correspond to an extension direction of the gate stack, that is, the vertical direction with respect to the substrate…”),
wherein, the memory transistors in the one vertical memory group share a vertically extended columnar gate structure (claim 1 of Zhu, “…a gate stack that extends vertically with respect to the substrate to pass through each of the plurality of device layers…”),
part or all of the columnar gate structures of vertical memory groups in a same row are connected to a same word line (figure 21 of Zhu, [0091]-[0092]/[0088] of Zhu, “…the contact portion 1039 may be electrically connected to a word line. A gate control signal may be applied to the gate conductor layer 1027 through the word line via the contact portion 1039…”),
part or all of the memory transistors located at a same stack layer in vertical memory groups in a same column are connected to a same bit line ([0092]-[0093] of Zhu, “…eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8…”, [0088] of Zhu, “…source/drain regions … electrically connected to the bit lines via the contact portion 1041 respectively…”), and
wherein, at least one column of the vertical memory groups includes i sub-columns of the vertical memory groups, where i is a natural number greater than 1 (Zhu teaches that preparatory layer sections may be divided into subsections 1103a and 1103b, [0111] of Zhu, “…Each section of the preparatory layer 1103 may be further divided…”, Zhu further teaches that more subsections, such as four subsections arranged in a 2x2 configuration, may be formed ([0112] of Zhu));
wherein the columnar gate structures of at least two adjacent sub-columns of the vertical memory groups are spaced in the column direction (figure 21 of Zhu shows regularly spaced gate stacks WL1, WL2 and WL3, Zhu [0094] teaches adjacent bit lines are isolated from each other. The periodic array layout inherently requires spacing between adjacent gate stacks, RAJASHEKHAR teaches in claim 1 memory openings and vertical stacks laterally separated from each other, thus adjacent vertical structures are spaced apart).
Regarding claim 7, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 6, wherein, an isolation part, for isolating active areas and bit lines of the memory transistors in the adjacent columns, is arranged between adjacent columns of the vertical memory groups (Zhu teaches isolation layers between device layers and isolation plugs, and adjacent bit line are isolated from each other, [0094] of Zhu, “…adjacent bit lines are isolated from each other...”, claim 9 of RAJASHEKHAR, “…insulating layers interlaced with the source layers and the drain layers of the alternating stack, wherein the insulating layers comprise: channel-level insulating layers in contact with a respective one of the semiconductor channels; and inter-transistor-level insulating layers located between vertically neighboring pairs of the channel-level insulating layers and not contacting any of the semiconductor channels…”, It would have been obvious to a person having ordinary skill in the art at the time of effective filing to incorporate RAJASHEKHAR’s insulating structure between adjacent vertical memory stacks into Zhu’s NOR memory array, in order to improve electrical isolation between adjacent memory components).
Regarding claim 8, the combination of Zhu and RAJASHEKHAR teaches a NOR memory, comprising a NOR memory array according to claim 1, and a write operation part, wherein, the write operation part is configured to apply a gate write voltage to a columnar gate structure of a vertical memory group to be written, and to apply a source voltage or a bit line write voltage to bit lines and source lines of the vertical memory group to be written, respectively (Zhu in [0091]-[0092] teaches a NOR type operation. In figure 21 and [0088] of Zhu, gate control signal applied to gate conductor layer via word line, Zhu in [0092] teaches bit lines and source lines connected to cells. In a NOR array, writing occurs by applying a voltage to a selected word line and bitline while holding other lines at bias potentials, thus Zhu teaches applying gate voltage, bitline voltage and source line voltage to create a voltage difference across selected transistor, RAJASHEKHAR teaches 3D NOR structure compatible with standard NOR writing scheme in claim 1), so that there is only a write voltage difference between two source/drain layers of a memory transistor in which data "0" is to be written (this is inherent in selective NOR programming. When programming one cell, only selected cell has full VDD while unselected cells are biased to avoid programming).
Regarding claim 9, the combination of Zhu and RAJASHEKHAR teaches a NOR memory, comprising a NOR memory array according to claim 6, and a write operation part, wherein, the write operation part is configured to apply a gate write voltage to a columnar gate structure of a vertical memory group to be written, and to apply a source voltage or a bit line write voltage to bit lines and source lines of the vertical memory group to be written, respectively (Zhu in [0091]-[0092] teaches a NOR type operation. In figure 21 and [0088] of Zhu, gate control signal applied to gate conductor layer via word line, Zhu in [0092] teaches bit lines and source lines connected to cells. In a NOR array, writing occurs by applying a voltage to a selected word line and bitline while holding other lines at bias potentials, thus Zhu teaches applying gate voltage, bitline voltage and source line voltage to create a voltage difference across selected transistor, RAJASHEKHAR teaches 3D NOR structure compatible with standard NOR writing scheme in claim 1), so that there is only a write voltage difference between two source/drain layers of a memory transistor in which data "0" is to be written (this is inherent in selective NOR programming. When programming one cell, only selected cell has full VDD while unselected cells are biased to avoid programming).
Regarding claim 10, the combination of Zhu and RAJASHEKHAR teaches a NOR memory, comprising a NOR memory array according to claim 1, and a read operation part, wherein, the read operation part is configured to apply a gate read voltage to a columnar gate structure of a vertical memory group to be read, and to apply a source voltage or a bit line read voltage to bit lines and source lines of the vertical memory group to be read, respectively, so that there is only a read voltage difference between two source/drain layers of one memory transistor to be read therein (Zhu in [0091]-[0092] teaches a NOR type operation. NOR read operation: apply read voltage to selected word line, apply small drain voltage, sense current on bitline, only selected cell sees full read bias. Unselected cells are biased to prevent conduction, RAJASHEKHAR teaches 3D NOR structure compatible with standard NOR writing/reading scheme in claim 1).
Regarding claim 11, the combination of Zhu and RAJASHEKHAR teaches a NOR memory, comprising a NOR memory array according to claim 6, and a read operation part, wherein, the read operation part is configured to apply a gate read voltage to a columnar gate structure of a vertical memory group to be read, and to apply a source voltage or a bit line read voltage to bit lines and source lines of the vertical memory group to be read, respectively, so that there is only a read voltage difference between two source/drain layers of one memory transistor to be read therein (Zhu in [0091]-[0092] teaches a NOR type operation. In figure 21 and [0088] of Zhu, gate control signal applied to gate conductor layer via word line, Zhu in [0092] teaches bit lines and source lines connected to cells. In a NOR array, NOR read operation: apply read voltage to selected word line, apply small drain voltage, sense current on bitline, only selected cell sees full read bias. Unselected cells are biased to prevent conduction, RAJASHEKHAR teaches 3D NOR structure compatible with standard NOR writing/reading scheme in claim 1).
Regarding claim 12, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory array according to claim 1 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 13, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory array according to claim 6 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 14, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory according to claim 8 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 15, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory according to claim 9 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 16, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory according to claim 10 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 17, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory according to claim 11 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824