Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 6/3/2026. The changes and remarks disclosed therein have been considered. Claims 1, 2, 4, 5, 7 have been amended. New Claim 29-18 has been added. Therefore, claims 1-18 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10, 12, 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu PG PUB 20230363153 (hereinafter Zhu), in view of RAJASHEKHAR PG PUB 20210202703 (hereinafter RAJASHEKHAR).
Regarding independent claim 1, Zhu teaches a NOR memory array (title of Zhu) comprising:
multiple vertical memory groups (figure 2(a), figure 11(a), figure 22(a), figure 25(a), [0031], “…In a plane where the device layer is located, these memory cells are arranged into an array (for example, generally, a two-dimensional array arranged in rows and columns) corresponding to the plurality of gate stacks…”) arranged in n rows (one planar direction in figure 2(a)) and m columns (another planar direction in figure 2(a)) on a horizontal plane, wherein each vertical memory group is located at an intersection of one of the rows and one of the columns (figure 2(a), figure 11(a), figure 22(a), figure 25(a), [0031]), each vertical memory group includes at least h vertically stacked memory transistors (10051-10054 in figure 22(a)), where n, m, and h are natural numbers greater than 1, and the vertical direction is perpendicular to the horizontal plane (figure 1, 3, [0029], [0031]-[0033]),
wherein, the memory transistors in the one each vertical memory group share a vertically extended columnar gate structure (gate stack 1027 extending through the vertical stacked device layers 10051-10054, figures 9-10, figure 25(d), [0031]/[0079]/[0114]),
all of the columnar gate structures of vertical memory groups in a same row are connected to a same word line (figure 21 of Zhu, WL1/WL2/WL3 are distinct word lines connected to respective gate stacks, [0088]/[0093]/[0114]), and different rows are connected to different word lines isolated from each other (Zhu teaches in figure 5, 10, [0060], [0065] isolation layers 10231-10234, WL1-WL3 are separate word line conductors associated with different rows and operate independently. The intervening dielectric structure pf the memory stack electrically isolate the word lines from one another),
all of the memory transistors located at a same stack layer in vertical memory groups in a same column are connected to a same bit line (figure 21 of Zhu, “…eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8…”, [0088] of Zhu, “…source/drain regions … electrically connected to the bit lines via the contact portion 1041 respectively…”) and different columns are connected to different bit lines isolated from each other (Zhu teaches in figure 5, 10, [0060], [0094], “…adjacent bit lines are isolated from each other…”), and an isolation part, is arranged between adjacent columns of the vertical memory groups in the horizontal plane (Zhu in figure 2(a), 3-10 shows processing channels and pillars separated laterally, the space between neighboring channels are physical dielectric regions).
However, Zhu does not explicitly teach an isolation part, is configured such that, at each stack layer, source regions, drain regions, and channel regions of memory transistors in the adjacent columns are laterally isolated from each other.
RAJASHEKHAR teaches insulating layers disposed between neighboring vertical memory structures to electrically isolate active semiconductor regions from adjacent vertical memory structures (claim 9, figure 10, [0109], claim 9 of RAJASHEKHAR, “…insulating layers interlaced with the source layers and the drain layers of the alternating stack, wherein the insulating layers comprise: channel-level insulating layers in contact with a respective one of the semiconductor channels; and inter-transistor-level insulating layers located between vertically neighboring pairs of the channel-level insulating layers and not contacting any of the semiconductor channels…”).
Both Zhu and RAJASHEKHAR are directed to three-dimensional NOR-type memory architectures employing vertically stacked device layers and vertical gate structures. The substitution of known isolation techniques from RAJASHEKHAR into Zhu’s structure would have been a predictable use of prior art elements according to their established function. It would have been obvious to a person having ordinary skill in the art at the time of effective filing to incorporate RAJASHEKHAR’s insulating structure into Zhu’s NOR memory array, in order to improve electrical isolation between adjacent memory components.
Regarding claim 2, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 1, wherein, each of the vertical memory group comprises h+1 source/drain layers and h channel layers alternately stacked in a vertical direction (claim 1 of Zhu, “…a plurality of device layers stacked on a substrate, wherein each of the plurality of device layers comprises a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first source/drain region and the second source/drain region in the vertical direction…”, [0031]/[0094] of Zhu, Zhu teaches alternating source/drain regions and channel regions stacked vertically, claim 1 of RAJASHEKHAR, “…an alternating stack of source layers and drain layers located over a substrate… vertical stacks of discrete semiconductor channels…”), wherein each of the channel layers is directly contacted, in the vertical direction, by two vertically adjacent source/drain layers with no intervening layer therebetween (Zhu teaches that each memory cell includes a channel region disposed between upper and lower source/drain regions, claim 1 of Zhu, figure 11© of Zhu), and each pair of vertically adjacent source/drain layers is separated by exactly one of the channel layers in the vertical direction with no intervening layer therebetween (Zhu teaches alternating source/drain and channel regions, [0073] fo Zhu), wherein each channel layer and two vertically adjacent source/drain layers directly contacted therewith in the vertical direction construct an active area of one memory transistor (Zhu teaches that each device layer forms a memory cell defined at a position where the gate conductor layer intersects a corresponding device layer via the memory function layer, claim 1 and [0114] of Zhu, each memory cell include a channel region between source/drain regions), wherein two adjacent memory transistors in the vertical direction share a common source/drain layer ([0092] of Zhu, “…every two adjacent device layers may share the same source line connection…”) and the h+1 source/drain layers are respectively connected to h+1 metal lines that construct the respective bit lines or source lines of the h memory transistors ([0092]/[0088] of Zhu, “…For every two adjacent memory cells in the vertical direction, source/drain regions located in the middle, i.e. the source/drain region 1009.sub.1 in the first device layer 1005.sub.1 and the source/drain region 1007.sub.2 in the second device layer 1005.sub.2, or the source/drain region 1009.sub.3 in the third device layer 1005.sub.3 and the source/drain region 1007.sub.4 in the fourth device layer 1005.sub.4, may be electrically connected to a source line via the common contact portion 1041... source/drain regions located at upper and lower ends, i.e. the source/drain region 1007.sub.1 in the first device layer 1005.sub.1 and the source/drain region 1009.sub.2 in the second device layer 1005.sub.2, or the source/drain region 1007.sub.3 in the third device layer 1005.sub.3 and the source/drain region 1009.sub.4 in the fourth device layer 1005.sub.4, may be electrically connected to the bit lines via the contact portion 1041 respectively…”)
Regarding claim 3, the combination of Zhu and RAJASHEKHAR teaches the NOR memory array according to claim 2, wherein, the vertical memory groups in the same column share the h+1 source/drain layers, and contacts for respectively connecting to the h+1 metal lines that construct the respective bit lines or source lines of the h memory transistors are respectively provided at ends of the source/drain layers of each column ([0087]-[0088] of Zhu, figure 18 of Zhu, claim 1 of RAJASHEKHAR).
Regarding claim 8, the combination of Zhu and RAJASHEKHAR teaches a NOR memory, comprising a NOR memory array according to claim 1, and a write operation part, wherein, the write operation part is configured to apply a gate write voltage to a columnar gate structure of a vertical memory group to be written, and to apply a source voltage or a bit line write voltage to bit lines and source lines of the vertical memory group to be written, respectively (Zhu in [0091]-[0092] teaches a NOR type operation. In figure 21 and [0088] of Zhu, gate control signal applied to gate conductor layer via word line, Zhu in [0092] teaches bit lines and source lines connected to cells. In a NOR array, writing occurs by applying a voltage to a selected word line and bitline while holding other lines at bias potentials, thus Zhu teaches applying gate voltage, bitline voltage and source line voltage to create a voltage difference across selected transistor, RAJASHEKHAR teaches 3D NOR structure compatible with standard NOR writing scheme in claim 1), so that there is only a write voltage difference between two source/drain layers of a memory transistor in which data "0" is to be written (this is inherent in selective NOR programming. When programming one cell, only selected cell has full VDD while unselected cells are biased to avoid programming).
Regarding claim 10, the combination of Zhu and RAJASHEKHAR teaches a NOR memory, comprising a NOR memory array according to claim 1, and a read operation part, wherein, the read operation part is configured to apply a gate read voltage to a columnar gate structure of a vertical memory group to be read, and to apply a source voltage or a bit line read voltage to bit lines and source lines of the vertical memory group to be read, respectively, so that there is only a read voltage difference between two source/drain layers of one memory transistor to be read therein (Zhu in [0091]-[0092] teaches a NOR type operation. NOR read operation: apply read voltage to selected word line, apply small drain voltage, sense current on bitline, only selected cell sees full read bias. Unselected cells are biased to prevent conduction, RAJASHEKHAR teaches 3D NOR structure compatible with standard NOR writing/reading scheme in claim 1).
Regarding claim 12, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory array according to claim 1 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 14, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory according to claim 8 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Regarding claim 16, the combination of Zhu and RAJASHEKHAR teaches an electronic device comprising a NOR memory according to claim 10 ([0117] of Zhu, “…memory device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, the memory device may store various programs, applications and data required for an operation of the electronic apparatus. The electronic apparatus may further include a processor cooperated with the memory device. For example, the processor may operate the electronic apparatus by running a program stored in the memory device. Such electronic apparatus includes, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply…”)
Response to Amendment
Applicant argues that Zhu and RAJASHEKHAR fail to teaches the limitations recited in amended claim 1:
Zhu figure 21 is a vertical-plane array, therefore it does not teach multiple vertical memory groups arranged in n rows and m columns on a horizontal plane;
Zhu’s “adjacent bit lines” of [0094] are vertical adjacent bit lines, not horizontal adjacent columns.
RAJASHEKHAR’s isolation layers are between vertically adjacent source/drain layers, not between horizontally adjacent columns.
Examiner respectful disagrees.
Regarding feature A (rows and columns on a horizontal plane).
Applicant focuses on figure 21 while ignoring Zhu’s disclosure of the physical memory device structure.
Zhu teaches in [0031] “In a plane where the device layer is located, these memory cells are arranged into an array (for example, generally, a two-dimensional array arranged in rows and columns) corresponding to the plurality of gate stacks”. Thus Zhu teaches a two dimensional row-column arrangement. Furthermore, figure 2(a), 11(A), 22(a), 23(b), 24(c), 25(c) are plan views showing memory openings arranged in orthogonal row and column directions on a horizontal plane.
The claims merely requires: multiple vertical memory groups arranged in n rows and m columns on a horizontal plane, and does not require word lines themselves to extend horizontally. Therefore, Zhu teaches the claimed row-column arrangement.
Regarding feature B (vertical memory group located at intersection of row and column)
Applicant argument is not persuasive.
A memory opening show in Zhu’s plan views occupies a unique row position and unique column position within the two-dimensional array. Each gate stack extending vertical through multiple device layer forms a vertical memory group. Therefore, each vertical memory group is located at the intersection of the one row and one column.
Regarding feature C (isolation between adjacent column)
Applicant argues that Zhu’s isolation layers only separate vertical adjacent device layers.
Applicant argument is not persuasive.
Zhu teaches physically separated memory opening arranged in row and columns on a horizontal plane, dielectric material between adjacent memory structures, and isolated adjacent bit lines ([0094]).
RAJASHEKHAR teaches in claim 9 “…insulating layers interlaced with the source layers and the drain layers of the alternating stack, wherein the insulating layers comprise: channel-level insulating layers in contact with a respective one of the semiconductor channels; and inter-transistor-level insulating layers located between vertically neighboring pairs of the channel-level insulating layers and not contacting any of the semiconductor channels…” RAJASHEKHAR further teaches insulating structures used to electrically isolate neighboring memory structures within a 3D NOR architecture.
It would have been obvious to incorporate the insulating structures of RAJASHEKHAR into Zhu’s array to improve electrical isolation, reduce parasitic coupling, and suppress leakage between adjacent memory structures.
Allowable Subject Matter
Claims 6-7, 9, 11, 13, 15, 17-18 are allowed.
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Zhu PG PUB 20230363153 (hereinafter Zhu).
Zhu discloses a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes a plurality of device layers. Each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first source/drain region and the second source/drain region; and a gate stack that extends vertically with respect to the substrate. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. The memory functional layer includes a first layer having a plurality of portions that correspond to the plurality of device layers respectively and are discontinuous with each other in the vertical direction.
Regarding claim 4 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein the columnar gate structures of at least two adjacent sub-columns of the vertical memory groups are staggered in the column direction.
Regarding independent claim 6 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein the columnar gate structures of at least two adjacent sub-columns of the vertical memory groups are staggered in the column direction.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOCHUN L CHEN/Examiner, Art Unit 2824
Prosecution Insights