DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-13 and 15-20 in the reply filed on 7/09/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim 14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/09/26.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/11/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US PGPub 2011/0079879, hereinafter referred to as “Cho”).
Cho discloses the semiconductor device as claimed. See figures 1-13 and corresponding text, where Cho teaches, in claim 1, a semiconductor structure, comprising:
a storage node pad array (150c), the storage node pad array comprising:
a plurality of first pads (142) separately disposed in a first direction and in a second direction; (figures 2C; [0069])
a first marginal pad disposed at one side of the storage node pad array, the first marginal pad comprising a plurality of first branch pads extending in the first direction;
a second marginal pad (142) disposed at another side of the storage node pad array being opposite to the first marginal pad, the second marginal pad comprising a plurality of second branch pads extending in the first direction;
a plurality of second pads (142) separately disposed between the first branch pads in a third direction; and
a plurality of third pads (142) separately disposed between the second branch pads in the third direction;
wherein a length of the second pads in the first direction is smaller than a length of the third pads in the first direction (figures 2C; [0069]).
Cho teaches, in claim 2, wherein one of the first pads is sandwiched between the second branch pads or between the third pads, and none of the first pads is sandwiched between the first branch pads or between the second pads (figures 2C; [0069]).
Cho teaches, in claim 3, wherein the first pads comprise a first length in the first direction, the second pads comprise a second length in the first direction, and the third pad comprise a third length in the first direction, wherein the first length, the second length and the third length are all different from each other (figures 2C; [0069]).
Cho teaches, in claim 4, wherein end-portions of each of the second pads and each of the first branch pads are aligned with each other in the third direction, and end-portions of each of the third pads and each of the second branch pads are partially misaligned with each other (figures 2C; [0069]).
Cho teaches, in claim 5, further comprising: a plug array disposed below the storage node pad array, and the plug array comprising: a plurality of plugs disposed below the first pads, the second pads and the third pads, wherein each of the first pads, each of the second pads, and each of the third pad at least partially overlap a corresponding one of the plugs underneath, respectively (figures 2C; [0069]).
Cho teaches, in claim 6, wherein a distance between a barycenter of one of the first pads being closest to the second pads, the first branch pads, the third pads or the second branch pads in the first direction, and a barycenter of one of the plugs corresponding thereto is greater than a distance between a barycenter of another one of the first pads and a barycenter of one of the plugs corresponding thereto (figures 2C; [0069]).
Cho teaches, in claim 7, a semiconductor structure, comprising:
a storage node pad array (150c), the storage node pad array comprising:
a plurality of first pads (142) separately arranged into a plurality of columns in a first direction, and arranged into a plurality of rows in a second direction;
a first marginal pad disposed at one side of the storage node pad array, the first marginal pad comprising a plurality of first branch pads; and
a second marginal pad disposed at another side of the storage node pad array being opposite to the first marginal pad, the second marginal pad comprising a plurality of second branch pads;
wherein the first pads within each of the columns closest to the first marginal pad comprises a first zigzag profile, the first pads within each of the columns closest to the second marginal pad comprises a second zigzag profile, and the second zigzag profile is different from the first zigzag profile (figures 2C; [0064] [0069]).
Cho teaches, in claim 8, wherein an opening of the first zigzag profile is greater than an opening of the second zigzag profile (figures 2C; [0069]).
Cho teaches, in claim 9, wherein a height of the first zigzag profile is greater than a height of the second zigzag profile (figures 2C; [0069]).
Cho teaches, in claim 10, the storage node pad array further comprising: a plurality of second pads separately disposed between the first branch pads in a third direction; and a plurality of third pads separately disposed between the second branch pads in the third direction, wherein the first pads comprise a first length in the first direction, the second pads comprise a second length in the first direction, the third pads comprise a third length in the first direction, and the first length, the second length, and the third length are all different from each other (figures 2C; [0069]).
Cho teaches, in claim 11, wherein one of the first pads is sandwiched between the second branch pads or between the third pads in the third direction, and none of the first pads is sandwiched between the first branch pads or between the second pads in the third direction (figures 2C; [0069]).
Cho teaches, in claim 12, further comprising:
a plug array comprising:
a plurality of plugs disposed below the first pads, the second pads and the third pads, wherein each of the first pads, each of the second pads, and each of the third pad at least partially overlap a corresponding one of the plugs underneath, respectively (figures 2C; [0069]).
Cho teaches, in claim 13, wherein a distance between a barycenter of one of the first pads being closest to the second pads, the first branch pads, the third pads or the second branch pads in the first direction, and a barycenter of one of the plugs corresponding thereto is greater than a distance between a barycenter of another one of the first pads and a barycenter of one of the plugs corresponding thereto (figures 2C; [0069]).
Cho teaches, in claim 15, adjusting the pads further comprising: defining an angle between the pad-barycenter of one of the pads, and the plug-barycenter and the predicted pad-barycenter corresponding thereto; and modifying the one of the pads or keeping the one of the pads through the angle (figures 2C; [0069]).
Cho teaches, in claim 16, further comprising: forming a storage node pad array, the storage node pad array comprising: a plurality of first pads separately arranged into a plurality of columns in a first direction, and a plurality of rows in a second direction; a plurality of second pads arranged at a first side of the first pads; and a plurality of third pads arranged at a second side of the first pads, wherein the first pads comprise a first length in the first direction, the second pads comprise a second length in the first direction, the third pads comprise a third length in the first direction, and the first length, the second length, and the third length are all different from each other (figures 2C; [0069]).
Cho teaches, in claim 17, further comprising: keeping the one of the pads while the angle is less than 90 degrees (figures 2C; [0069]).
Cho teaches, in claim 18, further comprising: modify the one of the pads while the angle is greater than 90 degrees (figures 2C; [0069]).
Cho teaches, in claim 19, modifying the pad further comprising: additionally forming a column of the first pads being aligned with each other in the third direction, on the plugs (figures 2C; [0069]).
Cho teaches, in claim 20, modifying the pad further comprising: removing the first pads closest to the second pads or the third pads in the first direction (figures 2C; [0069]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 19, 2026
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