DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-13, in the reply filed on 8/7/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Min et al. (US 2022/0199549).
Regarding claim 1, Min discloses an electronic device, comprising:
a first conductive layer (41, fig. 9 and paragraphs 0059-0061);
a first insulating layer disposed on the first conductive layer (73, fig. 9 and paragraph 0060), wherein in a cross-sectional view of the electronic device, the first insulating layer has two side-surfaces which are opposite to each other (right side, left side, 73, fig. 9 and paragraph 0060);
a second insulating layer disposed on the first insulating layer and in contact with
the two side-surfaces of the first insulating layer (18, fig. 9 and paragraph 0061);
a second conductive layer disposed on the second insulating layer and electrically
connected to the first conductive layer (52, fig. 9 and paragraph 0063);
a plurality of semiconductor elements disposed on and electrically connected to
the second conductive layer (56, fig. 9 and paragraph 0062); and
a covering layer disposed on the plurality of semiconductor elements (30, fig. 9 and paragraph 0066).
Regarding claim 2, Min further discloses an adhesive layer disposed between the covering layer and the plurality of semiconductor elements (20, fig. 9 and paragraph 0029).
Regarding claim 3, Min further discloses wherein, in the cross-sectional view of the electronic device, the second insulating layer has two side-surfaces which are opposite to each other, and the adhesive layer contacts the two side-surfaces of the second insulating layer (18, fig. 9 and paragraph 0055).
Regarding claim 4, Min further discloses wherein the covering layer is configured to encapsulate the plurality of semiconductor elements (30, fig. 9).
Regarding claim 5, Min further discloses wherein, in the cross-sectional view of the electronic device, the second insulating layer has two side-surfaces which are opposite to each other, and the covering layer contacts the two side-surfaces of the second insulating layer (18, fig. 9 and paragraph 0055).
Regarding claim 6, Min further discloses wherein, in the cross-sectional view of the electronic device, the covering layer is greater than the second insulating layer in width (fig. 9).
Regarding claim 7, Min further discloses wherein the plurality of semiconductor elements comprise at least one of light emitting elements, integrated circuit chips, and passive components (56, fig. 9 and paragraph 0052).
Regarding claim 8, Min further discloses a shielding layer (30a, fig. 3C and paragraph 0033) disposed between the covering layer (30b, fig. 3C and paragraph 0033) and the second insulating layer (18, fig. 9),
wherein the shielding layer has a plurality of through-holes, and at least one of the
plurality of semiconductor elements is disposed in one of the plurality of
through-holes (from bottom, fig. 9).
Regarding claim 9, Min further discloses an adhesive layer disposed between the covering layer and the shielding layer (paragraphs 0028-0029).
Regarding claim 10, Min further discloses wherein, in the cross-sectional view of the electronic device, the second insulating layer has two side-surfaces which are opposite to each other, the shielding layer has two outside-surfaces, and the adhesive layer contacts the two side-surfaces of the second insulating layer and the two outside-surfaces of the shielding layer (20, 18, 30, fig. 9 and paragraph 0055).
Regarding claim 11, Min further discloses wherein the covering layer is configured to encapsulate the shielding layer (30b covers 30a, fig. 3C and paragraph 0033).
Regarding claim 12, Min further discloses wherein, in the
cross-sectional view of the electronic device, the second insulating layer has two
side-surfaces which are opposite to each other, the shielding layer has two
outside-surfaces, and the covering layer contacts the two side-surfaces of the second
insulating layer and the two outside-surfaces of the shielding layer (20, 18, 30, fig. 9 and paragraph 0055).
Regarding claim 13, Min further discloses wherein one of the
plurality of semiconductor elements is different from another one of the plurality of
semiconductor elements in function (paragraph 0083).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2019/0326223 discloses a relevant semiconductor package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 9/19/26
Prosecution Insights