DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11721547 (Hecht et al).
Concerning claim 1, Hecht discloses a silicon carbide wafer manufacturing method comprising (Figs. 2A-2E): forming a silicon carbide epitaxial layer (220) on a first silicon carbide substrate (210) (col. 7 lines 14-20); using an ion implantation process (230) to form a thermal separation layer in the silicon carbide epitaxial layer (col. 7 lines 23-24); using a temporary substrate (250) to bond the silicon carbide epitaxial layer (Fig. 2C); heating the silicon carbide epitaxial layer causes the thermal separation layer to decompose and the silicon carbide epitaxial layer is separated into an upper silicon carbide epitaxial layer and a lower silicon carbide epitaxial layer (col. 6 lines 54-62); and performing a first chemical mechanical polishing process on the upper silicon carbide epitaxial layer bonded to the temporary substrate (col. 5 lines 34-41).
Continuing to claim 2, Hecht discloses wherein ions used in the ion implantation process comprise hydrogen ions (col. 6 lines 10-16).
Considering claim 3, Hecht discloses wherein ions used in the ion implantation process comprise helium ions (col. 6 lines 10-16).
Referring to claim 5, Hecht discloses wherein an extension direction of the thermal separation layer is perpendicular to a central axis of the first silicon carbide substrate (col. 6 lines 27-37).
Regarding claim 9, Hecht discloses further comprising: performing a second chemical mechanical polishing process on the lower silicon carbide epitaxial layer bonded to the first silicon carbide substrate (col. 2 lines 45-48, note that it is disclosed that CMP is done between multiple transfers in order to be able to reuse the transfer substrate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240055251 (Csato et al) in view of US 20150214040 (Celler).
Regarding claim 1, Csato discloses a silicon carbide wafer manufacturing method comprising (Figs. 1-13 and 15): forming a silicon carbide epitaxial layer (16/21) on a first silicon carbide substrate (14/22) ([0122]); using an ion implantation process to form a thermal separation layer (26) in the silicon carbide epitaxial layer ([0145]); using a temporary substrate (28) to bond the silicon carbide epitaxial layer (Fig. 11); heating the silicon carbide epitaxial layer causes the thermal separation layer to decompose and the silicon carbide epitaxial layer is separated into an upper silicon carbide epitaxial layer and a lower silicon carbide epitaxial layer (Fig. 12 and [0157]); and performing a first . . . polishing process on the upper silicon carbide epitaxial layer bonded to the temporary substrate ([0160]).
Csato does not disclose that the polishing process is a chemical mechanical polishing process. However, Celler discloses a method of manufacturing a silicon carbide wafer in which a chemical mechanical polishing (CMP) process is used as a surface treatment after transferring a silicon carbide epitaxial layer by ion implantation cleaving ([0046]). CMP is a known polishing process that can be used as a surface treatment after a transfer process as disclosed by Hecht, and therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a chemical mechanical polishing process as the polishing process of Csato because of its known suitability as a surface treatment after transfer done by cleaving.
Pertaining to claim 2, Csato in view of Celler disclose wherein ions used in the ion implantation process comprise hydrogen ions (Csato [0145]).
As to claim 3, Csato in view of Celler disclose wherein ions used in the ion implantation process comprise helium ions (Csato [0145]).
Concerning claim 4, Csato in view of Celler disclose wherein the silicon carbide epitaxial layer is a single-crystal silicon carbide epitaxial layer (Csato [0016]).
Continuing to claim 5, Csato in view of Celler discloses wherein an extension direction of the thermal separation layer is perpendicular to a central axis of the first silicon carbide substrate (Csato Fig. 11).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240055251 (Csato et al) in view of US 20150214040 (Celler) as applied to claim 1 above, and further in view of US 20130037854 (Von Kanel et al).
Considering claim 6, Csato in view of Celler disclose forming a silicon carbide.
Csato in view of Celler as disclosed above does not disclose further comprising: bonding a second silicon carbide substrate on the upper silicon carbide epitaxial layer bonded to the temporary substrate, wherein the temporary substrate and the second silicon carbide substrate are located on two opposite sides of the upper silicon carbide epitaxial layer. However, Celler discloses a manufacturing process for a SiC substrate that discloses further comprising: bonding a second substrate (240) on the upper silicon carbide epitaxial layer bonded to the temporary substrate (211), wherein the temporary substrate and the second silicon carbide substrate are located on two opposite sides of the upper silicon carbide epitaxial layer (Figs. 2E-2I and [0029]-[0041]), and such process yields thin device wafers can be generated through epitaxial SiC instead of requiring wafer thinning by grinding to improve device performance ([0019]). Celler discloses that the substrate is a CMOS substrate made of Si, but Von Kanel discloses that Si, SiC, etc. are also suitable as CMOS substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the process of Csato to further comprise: performing a second chemical mechanical polishing process on the lower silicon carbide epitaxial layer bonded to the first silicon carbide substrate in order to provide a thin device wafers can be generated through epitaxial SiC instead of requiring wafer thinning by grinding to improve device performance as disclosed by Celler.
Referring to claim 7, Csato in view of Celler and Von Kanel disclose further comprising: removing the temporary substrate such that the upper silicon carbide epitaxial layer is located on the second silicon carbide substrate (Celler Figs. 2F-2I and [0039]-[0041]).
Regarding claim 8, Csato in view of Celler and Von Kanel disclose further comprising: performing a second chemical mechanical polishing process on the upper silicon carbide epitaxial layer bonded to the second silicon carbide substrate (Celler [0038]).
Claim(s) 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240055251 (Csato et al) in view of US 20150214040 (Celler) and US 20130037854 (Von Kanel et al).
Pertaining to claim 10, Csato discloses a silicon carbide wafer manufacturing method comprising (Figs. 1-13 and 15): forming a silicon carbide epitaxial layer (16/21) on a first silicon carbide substrate (14/22) ([0122]); using an ion implantation process to form a thermal separation layer (26) in the silicon carbide epitaxial layer ([0145]); using a temporary substrate (28) to bond the silicon carbide epitaxial layer (Fig. 11); heating the silicon carbide epitaxial layer causes the thermal separation layer to decompose and the silicon carbide epitaxial layer is separated into an upper silicon carbide epitaxial layer and a lower silicon carbide epitaxial layer (Fig. 12 and [0157]); and performing a first . . . polishing process on the upper silicon carbide epitaxial layer bonded to the temporary substrate ([0160]).
Csato does not disclose that the polishing process is a chemical mechanical polishing process or bonding a second silicon carbide substrate to a surface of the upper silicon carbide epitaxial layer that is processed by the first chemical mechanical polishing process. However, Celler discloses a method of manufacturing a silicon carbide wafer in which a chemical mechanical polishing (CMP) process is used as a surface treatment after transferring a silicon carbide epitaxial layer by ion implantation cleaving ([0046]). CMP is a known polishing process that can be used as a surface treatment after a transfer process as disclosed by Hecht. Additionally, Celler discloses a manufacturing process for a SiC substrate that discloses further comprising: bonding a second substrate (240) on the upper silicon carbide epitaxial layer bonded to the temporary substrate (211), wherein the temporary substrate and the second silicon carbide substrate are located on two opposite sides of the upper silicon carbide epitaxial layer (Figs. 2E-2I and [0029]-0041]), and such process yields thin device wafers can be generated through epitaxial SiC instead of requiring wafer thinning by grinding to improve device performance ([0019]). Celler discloses that the substrate is a CMOS substrate made of Si, but Von Kanel discloses that Si, SiC, etc. are also suitable as CMOS substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the process of Csato to use a chemical mechanical polishing process as the polishing process of Csato because of its known suitability as a surface treatment after transfer done by cleaving and further comprise: performing a second chemical mechanical polishing process on the lower silicon carbide epitaxial layer bonded to the first silicon carbide substrate in order to provide a thin device wafers can be generated through epitaxial SiC instead of requiring wafer thinning by grinding to improve device performance as disclosed by Celler.
As to claim 11, Csato in view of Celler and Von Kanel disclose wherein the temporary substrate and the second silicon carbide substrate are located on two opposite sides of the upper silicon carbide epitaxial layer (Celler Figs. 2F-2I and [0039]-[0041]).
Concerning claim 12, Csato in view of Celler and Von Kanel disclose wherein ions used in the ion implantation process comprise hydrogen ions, helium ions or a combination thereof (Csato [0145]).
Continuing to claim 13, Csato in view of Celler and Von Kanel disclose wherein the silicon carbide epitaxial layer is a single-crystal silicon carbide epitaxial layer (Csato [0016]).
Referring to claim 14, Csato in view of Celler and Von Kanel discloses wherein an extension direction of the thermal separation layer is perpendicular to a central axis of the first silicon carbide substrate (Csato Fig. 11).
Regarding claim 15, Csato in view of Celler and Von Kanel discloses further comprising: removing the temporary substrate such that the upper silicon carbide epitaxial layer is located on the second silicon carbide substrate (Celler Figs. 2E-2I and [0039]-[0041]).
Pertaining to claim 16, Csato discloses a silicon carbide wafer manufacturing method comprising (Figs. 1-13 and 15): forming a silicon carbide epitaxial layer (16/21) on a first silicon carbide substrate (14/22) ([0122]); using an ion implantation process to form a thermal separation layer (26) in the silicon carbide epitaxial layer ([0145]); using a temporary substrate (28) to bond the silicon carbide epitaxial layer (Fig. 11); heating the silicon carbide epitaxial layer causes the thermal separation layer to decompose and the silicon carbide epitaxial layer is separated into an upper silicon carbide epitaxial layer and a lower silicon carbide epitaxial layer (Fig. 12 and [0157]); and performing a first . . . polishing process on the upper silicon carbide epitaxial layer bonded to the temporary substrate ([0160]).
Csato does not disclose that the polishing process is a chemical mechanical polishing process or bonding a second silicon carbide substrate to a surface of the upper silicon carbide epitaxial layer that is processed by the first chemical mechanical polishing process; and removing the temporary substrate and performing a second chemical mechanical polishing process on an exposed surface of the upper silicon carbide epitaxial layer. However, Celler discloses a method of manufacturing a silicon carbide wafer in which a chemical mechanical polishing (CMP) process is used as a surface treatment after transferring a silicon carbide epitaxial layer by ion implantation cleaving ([0046]). CMP is a known polishing process that can be used as a surface treatment after a transfer process as disclosed by Hecht. Additionally, Celler discloses a manufacturing process for a SiC substrate that discloses further comprising: bonding a second substrate (240) on the upper silicon carbide epitaxial layer to a surface of the upper silicon carbide epitaxial layer that is processed by the first chemical mechanical polishing process (Fig. 2E and [0036]), removing the temporary substrate and performing a second chemical mechanical polishing process on an exposed surface of the upper silicon carbide epitaxial layer (Figs. 2F-2I and [0038]), and such process yields thin device wafers can be generated through epitaxial SiC instead of requiring wafer thinning by grinding to improve device performance ([0019]). Celler discloses that the substrate is a CMOS substrate made of Si, but Von Kanel discloses that Si, SiC, etc. are also suitable as CMOS substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the process of Csato to use a chemical mechanical polishing process as the polishing process of Csato because of its known suitability as a surface treatment after transfer done by cleaving and further comprise: performing a second chemical mechanical polishing process on the lower silicon carbide epitaxial layer bonded to the first silicon carbide substrate in order to provide a thin device wafers can be generated through epitaxial SiC instead of requiring wafer thinning by grinding to improve device performance as disclosed by Celler.
As to claim 17, Csato in view of Celler and Von Kanel disclose wherein ions used in the ion implantation process comprise hydrogen ions, helium ions or a combination thereof (Csato [0145]).
Concerning claim 18, Csato in view of Celler and Von Kanel disclose wherein the silicon carbide epitaxial layer is a single-crystal silicon carbide epitaxial layer (Csato [0016]).
Continuing to claim 19, Csato in view of Celler and Von Kanel discloses wherein an extension direction of the thermal separation layer is perpendicular to a central axis of the first silicon carbide substrate (Csato Fig. 11).
Considering claim 20, Csato in view of Celler and Von Kanel discloses further comprising: performing a third chemical mechanical polishing process on the lower silicon carbide epitaxial layer bonded to the first silicon carbide substrate (Celler [0038]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230009774 discloses a composite substrate manufacturing method (Fig. 5A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 06/09/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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