DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/28/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argued that the prior art does not disclose the amended limitation specially the limitation “wherein a side surface of the second light emitter overlaps in plan view with a majority of a side surface of the first light emitter and a different side surface of the second light emitter overlaps in the plan view with a majority of a side surface of the third light emitter.”
However as shown in the rejection below, Figs 1-2 and 19 of prior art Takeya discloses the amended limitation. Therefore, the prior art Takeya discloses the entire claimed invention of claim 1.
Regarding claim 8, Applicant argued that the prior art does not disclose the amended limitation specially the limitation “wherein a side surface of the second light emitter overlaps in plan view with a majority of a side surface of the first light emitter and a different side surface of the second light emitter overlaps in the plan view with a majority of a side surface of the third light emitter.”
However as shown in the rejection below, Figs 1-2 and 19 of prior art Takeya discloses the amended limitation. Therefore, the prior art Takeya discloses the entire claimed invention of claim 1.
Regarding claim 14, Applicant argued that the prior art does not disclose the amended limitation specially the limitation “wherein a side surface of the second light emitter overlaps in plan view with a majority of a side surface of the first light emitter and a different side surface of the second light emitter overlaps in the plan view with a majority of a side surface of the third light emitter.”
However as shown in the rejection below, Figs 1-2 and 19 of prior art Takeya discloses the amended limitation. Therefore, the prior art Takeya discloses the entire claimed invention of claim 1.
For above mentioned reasons, rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeya et al (US 2019/0229097; hereinafter Takeya).
Regarding claim 1, Figs 1B, 2 and 19 of Takeya discloses a light emitting device comprising:
a substrate (10; Figs 1B; ¶ [0100]);
a plurality of light emitters (150a (111a)/150b (111b)/150c (111c); Figs 1B/19; ¶ [0106]) disposed on the substrate (10; Figs 1B; ¶ [0100]), each of the plurality of light emitters including a first type semiconductive layer (153; Fig 2; ¶ [0133]), a second type semiconductive layer (157; Fig 2; ¶ [0132]), and an active layer (155; Fig 2; ¶ [0132]) disposed between the first type semiconductive layer (153; Fig 2; ¶ [0133]) and the second type semiconductive layer (157; Fig 2; ¶ [0132]);
a plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]), each of the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) including a first electrode (159p; Fig 2; ¶ [0127]) electrically connected to the first type semiconductive layer (153; Fig 2; ¶ [0133]) and a second electrode (159q; Fig 2; ¶ [0127]) electrically connected to the second type semiconductive layer (157; Fig 2; ¶ [0132]); and
conductive layers (170; Fig 2; ¶ [0106]) electrically connected to the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]),
wherein the plurality of light emitters (150a (111a)/150b (111b)/150c (111c); Figs 1B/19; ¶ [0106]) includes a first light emitter (150a (111a); Figs 1B/19; ¶ [0106]), a second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and a third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein a side surface (Left side of 111b; Fig 19) of the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]) overlaps in plan view (Fig 19) with a majority of a side surface (Right side of 111a; Fig 19) of the first light emitter (150a (111a); Figs 1B/19; ¶ [0106]) and a different side surface (Right side of 111b; Fig 19) of the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]) overlaps in the plan view with a majority of a side surface (Left side of 111c; Fig 19) of the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) includes a first set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the first light emitter (150a (111a); Figs 1B/19; ¶ [0106]), a second set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and a third set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein each connection layer (159q/159p/171a/171d; Fig 2; ¶ [0132]) of the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) includes a pad region (171a/171d; Fig 2; ¶ [0129]) connected to at least one of the first light emitter (150a; Fig 1B; ¶ [0106]), the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),,
wherein each of the conductive layers (170; Fig 2; ¶ [0106]) is connected to the pad region (171a/171d; Fig 2; ¶ [0129]) of each of the connection layers, respectively, and wherein the conductive layers (170; Fig 2; ¶ [0106]) are spaced apart (Fig 2) from one another.
Regarding claim 2, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) are spaced apart from the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]).
Regarding claim 3, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) include a region exposed to an outside (Fig 2).
Regarding claim 4, Figs 1B, 2 of Takeya discloses an insulating layer (163; Fig 2; ¶ [0126]) covering the plurality of sets of connection layers (170; Fig 2; ¶ [0106]).
Regarding claim 5, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) include a region covered (Fig 2) by the insulation layer (163; Fig 2; ¶ [0126]).
Regarding claim 6, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) are formed with the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]).
Regarding claim 7, Figs 1B, 2 of Takeya discloses the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]) include a blue light emitter (150a; Fig 1B; ¶ [0106]), a green light emitter (150b; Fig 1B; ¶ [0106]) and a red light emitter (150c; Fig 1B; ¶ [0106]).
Regarding claim 8, Figs 1B, 2 of Takeya discloses a light emitting device comprising:
a substrate (10; Figs 1B; ¶ [0100]);
light emitters (150a (111a)/150b (111b)/150c (111c); Figs 1B/19; ¶ [0106]) disposed on the substrate (10; Figs 1B; ¶ [0100]), each of the light emitters including a first type semiconductive layer (153; Fig 2; ¶ [0133]), a second type semiconductive layer (157; Fig 2; ¶ [0132]), and an active layer (155; Fig 2; ¶ [0132]) disposed between the first type semiconductive layer (153; Fig 2; ¶ [0133]) and the second type semiconductive layer (157; Fig 2; ¶ [0132]);
a plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]), each of the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) including a first electrode (159p; Fig 2; ¶ [0127]) electrically connected to the first type semiconductive layer (153; Fig 2; ¶ [0133]) and a second electrode (159q; Fig 2; ¶ [0127]) electrically connected to the second type semiconductive layer (157; Fig 2; ¶ [0132]); and
conductive layers (170; Fig 2; ¶ [0106]) electrically connected to the light emitters (150a/150b/150c; Fig 1B; ¶ [0106]),
wherein the plurality of light emitters (150a (111a)/150b (111b)/150c (111c); Figs 1B/19; ¶ [0106]) includes a first light emitter (150a (111a); Figs 1B/19; ¶ [0106]), a second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and a third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein a side surface (Left side of 111b; Fig 19) of the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]) overlaps in plan view (Fig 19) with a majority of a side surface (Right side of 111a; Fig 19) of the first light emitter (150a (111a); Figs 1B/19; ¶ [0106]) and a different side surface (Right side of 111b; Fig 19) of the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]) overlaps in the plan view with a majority of a side surface (Left side of 111c; Fig 19) of the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) includes a first set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the first light emitter (150a (111a); Figs 1B/19; ¶ [0106]), a second set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and a third set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein each of the conductive layers (170; Fig 2; ¶ [0106]) is connected to each of the connection layers respectively,
wherein conductive layers (170; Fig 2; ¶ [0106]) are formed with the plurality of sets of connection layers, and
wherein conductive layers (170; Fig 2; ¶ [0106]) are spaced apart from one another.
Regarding claim 9, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) are spaced apart from the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]).
Regarding claim 10, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) include a region exposed to an outside (Fig 2).
Regarding claim 11, Figs 1B, 2 of Takeya discloses an insulating layer (163; Fig 2; ¶ [0126]) covering the plurality of sets of connection layers (170; Fig 2; ¶ [0106]).
Regarding claim 12, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) include a region covered (Fig 2) by the insulation layer (163; Fig 2; ¶ [0126]).
Regarding claim 13, Figs 1B, 2 of Takeya discloses the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]) include a blue light emitter (150a; Fig 1B; ¶ [0106]), a green light emitter (150b; Fig 1B; ¶ [0106]) and a red light emitter (150c; Fig 1B; ¶ [0106]).
Regarding claim 14, Figs 1B, 2 of Takeya discloses a light emitting device comprising:
a substrate (10; Figs 1B; ¶ [0100]);
light emitters (150a (111a)/150b (111b)/150c (111c); Figs 1B/19; ¶ [0106]) disposed on the substrate (10; Figs 1B; ¶ [0100]), each of the light emitters including a first type semiconductive layer (153; Fig 2; ¶ [0133]), a second type semiconductive layer (157; Fig 2; ¶ [0132]), and an active layer (155; Fig 2; ¶ [0132]) disposed between the first type semiconductive layer (153; Fig 2; ¶ [0133]) and the second type semiconductive layer (157; Fig 2; ¶ [0132]);
a plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]), each of the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) including a first electrode (159p; Fig 2; ¶ [0127]) electrically connected to the first type semiconductive layer (153; Fig 2; ¶ [0133]) and a second electrode (159q; Fig 2; ¶ [0127]) electrically connected to the second type semiconductive layer (157; Fig 2; ¶ [0132]); and
conductive layers (170; Fig 2; ¶ [0106]) electrically connected to the light emitters (150a/150b/150c; Fig 1B; ¶ [0106]),
wherein the plurality of light emitters (150a (111a)/150b (111b)/150c (111c); Figs 1B/19; ¶ [0106]) includes a first light emitter (150a (111a); Figs 1B/19; ¶ [0106]), a second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and a third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein a side surface (Left side of 111b; Fig 19) of the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]) overlaps in plan view (Fig 19) with a majority of a side surface (Right side of 111a; Fig 19) of the first light emitter (150a (111a); Figs 1B/19; ¶ [0106]) and a different side surface (Right side of 111b; Fig 19) of the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]) overlaps in the plan view with a majority of a side surface (Left side of 111c; Fig 19) of the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) includes a first set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the first light emitter (150a (111a); Figs 1B/19; ¶ [0106]), a second set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the second light emitter (150b (111b); Figs 1B/19; ¶ [0106]), and a third set of connection layers (159q/159p; Fig 2; ¶ [0132]) electrically connected to the third light emitter (150c (111c); Figs 1B/19; ¶ [0106]),
wherein each connection layer (159q/159p/171a/171d; Fig 2; ¶ [0132]) of the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]) includes a pad region (171a/171d; Fig 2; ¶ [0129]) connected to at least one of the first light emitter (150a; Fig 1B; ¶ [0106]), the second light emitter (150b; Fig 1B; ¶ [0106]), and the third light emitter (150c; Fig 1B; ¶ [0106]),
wherein each of the conductive layers (170; Fig 2; ¶ [0106]) is connected to each of the connection layers respectively, and
wherein conductive layers (170; Fig 2; ¶ [0106]) are spaced apart from one another.
Regarding claim 15, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) are spaced apart from the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]).
Regarding claim 16, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) include a region exposed to an outside (Fig 2).
Regarding claim 17, Figs 1B, 2 of Takeya discloses an insulating layer (163; Fig 2; ¶ [0126]) covering the plurality of sets of connection layers (170; Fig 2; ¶ [0106]).
Regarding claim 18, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) include a region covered (Fig 2) by the insulation layer (163; Fig 2; ¶ [0126]).
Regarding claim 19, Figs 1B, 2 of Takeya discloses the conductive layers (170; Fig 2; ¶ [0106]) are formed with the plurality of sets of connection layers (159q/159p/171a/171d; Fig 2; ¶ [0132]).
Regarding claim 20, Figs 1B, 2 of Takeya discloses the plurality of light emitters (150a/150b/150c; Fig 1B; ¶ [0106]) include a blue light emitter (150a; Fig 1B; ¶ [0106]), a green light emitter (150b; Fig 1B; ¶ [0106]) and a red light emitter (150c; Fig 1B; ¶ [0106]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
