DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 12 April 2024. The references cited on the PTOL 1449 form have been considered.
Specification
The disclosure is objected to because of the following informalities:
Throughout the entire disclosure (written description and claims) it’s confusing to refer to both a plurality of lower semiconductor chips as a “lower semiconductor chip” and each individual lower semiconductor chip as a “lower semiconductor chip” having the same reference label, and likewise to refer to both a plurality of upper semiconductor chips as a “upper semiconductor chip” and each individual lower semiconductor chip as a “upper semiconductor chip” having the same reference label.
The examiner suggests that when referencing the group or collective of chips an acceptable reference label would be to refer to “a lower semiconductor chip structure” or “an upper semiconductor chip structure,” respectively. The lower semiconductor chip structure comprises a plurality of lower semiconductor chips and the upper semiconductor chip structure comprises a plurality of upper semiconductor chips.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s):
Claim 1 (and 2-14) – the “plurality of upper semiconductor chips” and “scribe lane” and relative structural relationships with respect to other elements.
Claim 7 – “a horizontal distance between ones of the plurality of upper semiconductor chips” and relative structural relationships with respect to other elements.
Claim 15 (and 16-18) – the “plurality of first semiconductor chips” and “scribe lane” and relative structural relationships with respect to other elements.
Claim 19 (and 20) – the “plurality of upper semiconductor chips” and “scribe lane” and relative structural relationships with respect to other elements.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites multiple instances of “the lower semiconductor chip,” which makes unclear which of the plurality of lower semiconductor chips is being referenced. It’s confusing throughout the entire disclosure (written description and claims) to refer to both a plurality of lower semiconductor chips as a “lower semiconductor chip” and each individual lower semiconductor chip as a “lower semiconductor chip” having the same reference label. In keeping with the manner in which the claim is intended to be written, an example of a clear recitation could be to reference “a lower semiconductor chip structure” comprising a plurality of lower semiconductor chips
Similarly, claim 1 also recites multiple instances of “the upper semiconductor chip,” which makes unclear which of the plurality of upper semiconductor chips is being referenced. It’s confusing throughout the entire disclosure (written description and claims) to refer to both a plurality of upper semiconductor chips as an “upper semiconductor chip” and each individual upper semiconductor chip as an “upper semiconductor chip” having the same reference label. In keeping with the manner in which the claim is intended to be written, an example of a clear recitation could be to reference “an upper semiconductor chip structure” comprising a plurality of upper semiconductor chips.
Claims 2-14 include the limitations and do not cure the deficiencies of claim 1. Many of the dependent claims also recite “the upper semiconductor chip” (claims 2, 3, 13 and 14) and/or “the lower semiconductor chip” (claims 11 and 14) which makes unclear which of the plurality of upper semiconductor chips and which of the plurality of lower semiconductor chips is being referenced.
Claim 19 recites “the lower semiconductor chip,” at line 19-20 of page 5, which makes unclear which of the plurality of lower semiconductor chips is being referenced. Claim 20 includes the limitations and do not cure the deficiencies of claim 19.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 4-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. Patent Application Publication 2021/0050300).
As insofar as Claim 1 is definite, Lin teaches in Fig. 36A and 41B (par. 723-732) a semiconductor package (306) comprising: a base substrate (100) having a lower redistribution layer (27); a lower semiconductor chip (lower 301; chip package) comprising a plurality of lower semiconductor chips (100; see Fig. 36A and par. 724; “may include two first type of chip packages 301, each of which may have the similar structure to that as illustrated in FIG. 36A, stacked with each other, i.e., top and bottom ones, and an non-volatile-memory (NVM) chip package 336 stacked on the bottom one of its first type of chip packages 301. For an element indicated by the same reference number shown in FIGS. 36A and 41A, the specification of the element as seen in FIG. 41A may be referred to that of the element as illustrated in FIG. 36A.” and par. 726; “the bottom one of its first type of chip packages 301 may include one or more first type of semiconductor chips 100 used for logic integrated-circuit (IC) chips 326, such as FPGA IC chip, graphic-processing unit (GPU) chip, central-processing-unit (CPU) chip or digital-signal-processing (DSP) chip”) having a first active surface (bottom) and first connection pads (Fig. 34A; par. 651, 658, 659) on the first active surface (bottom), wherein the plurality of lower semiconductor chips (100) are on the base substrate (101) such that the first active surface (bottom) faces an upper surface (top) of the base substrate (101), and wherein each of the first connection pads is electrically connected to the lower redistribution layer (27); an upper semiconductor chip (upper 301 comprising plurality of 100; par. 732) having a second active surface (bottom) and second connection pads (Fig. 34A; par. 651, 658, 659) on the second active surface (bottom), wherein the upper semiconductor chip (upper 301) is on the lower semiconductor chip (lower 301) such that the second active surface (bottom) faces the lower semiconductor chip (lower 301); an intermediate connection member (upper 101) on the second active surface (bottom) of the upper semiconductor chip (upper 301) and between the lower semiconductor chip (lower 301) and the upper semiconductor chip (upper 301), the intermediate connection member (upper 101) having an upper redistribution layer (27) electrically connected to each of the second connection pads; a plurality of vertical interconnectors (158) at least partially around the lower semiconductor chip (of lower 301) on the base substrate (lower 101) and electrically connecting the lower redistribution layer (lower 27) to the upper redistribution layer (upper 27); and a mold portion (92/257) on the base substrate (101) and having a first portion at least partially surrounding the lower semiconductor chip (lower 301) and the plurality of vertical interconnectors (158) and a second portion extending on the upper redistribution layer (upper 101) and side surfaces of the upper semiconductor chip (upper 301), wherein the upper semiconductor chip (upper 301) comprises a plurality of upper semiconductor chips (100), and one of the plurality of upper semiconductor chips is integrally connected (via upper 101 and 564) to an adjacent one of the plurality of upper semiconductor chips (100) with a scribe lane (indicated by arrow in the figure below) therebetween on a same plane (Fig. 41B).
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As insofar as Claim 2 is definite, Lin further teaches wherein the second portion of the mold portion (92/257) surrounds all side surfaces of the upper semiconductor chip (upper 301) and the intermediate connection member (upper 101).
As insofar as Claim 4 is definite, Lin further teaches wherein the intermediate connection member (upper 101) has a greater area than an active surface (bottom) of the one of the plurality of upper semiconductor chips (one of upper 100) and an active surface of the adjacent one of the plurality of upper semiconductor chips (another one of upper 100).
As insofar as Claim 5 is definite, Lin further teaches wherein the plurality of lower semiconductor chips (100 of lower 301) are separated from each other on the base substrate (lower 101).
As insofar as Claim 6 is definite, Lin further teaches wherein at least some of the plurality of vertical interconnectors (158) are between ones of the plurality of lower semiconductor chips (100 of lower 301; see Fig. 34A).
As insofar as Claim 7 is definite, Lin further teaches wherein a horizontal distance between ones of the plurality of lower semiconductor chips (left 100 and right 100 of lower 301) is different from a horizontal distance between ones of the plurality of upper semiconductor chips (100 of upper 301).
As insofar as Claim 8 is definite, Lin further teaches wherein the base substrate (lower 101) has a greater area than the intermediate connection member (upper 101).
As insofar as Claim 9 is definite, Lin further teaches wherein the base substrate (lower 101) has side surfaces that are substantially flat and coplanar with side surfaces of the mold portion (92/257).
As insofar as Claim 10 is definite, Lin further teaches wherein the upper redistribution layer (upper 27) comprises a plurality of redistribution patterns and a plurality of vias electrically connected to the plurality of redistribution patterns, and wherein at least some of the plurality of vias are electrically connected to the second connection pads (see Fig. 34A).
As insofar as Claim 11 is definite, Lin further teaches further comprising a plurality of conductive posts (34) on lower surfaces of the first connection pads, respectively, wherein the mold portion (92/257) has a third portion covering the first active surface of the lower semiconductor chip (lower 100), wherein the plurality of conductive posts (34) extend into the third portion of the mold portion (92/257), and wherein the lower redistribution layer (lower 27) is electrically connected to the plurality of conductive posts (34).
As insofar as Claim 12 is definite, Lin further teaches wherein the lower redistribution layer (lower 27) comprises a plurality of redistribution patterns and a plurality of vias electrically connected to the plurality of redistribution patterns, and wherein the plurality of vias comprise vias that contact the first connection pads (see Fig. 34A).
As insofar as Claim 13 is definite, Lin further teaches further comprising an external connection metal (upper 34) on the second active surface (bottom) of the upper semiconductor chip (100 of upper 301).
As insofar as Claim 14 is definite, Lin further teaches wherein the lower semiconductor chip (100 of lower 301) comprises a memory chip, and the upper semiconductor chip (100 of upper 301) comprises a processor chip (par. 677 and 732).
Referring to Claim 15, Lin teaches in Fig. 34A, 36A, 41A and 41B, a semiconductor package comprising: a plurality of first semiconductor chips (100 of upper 301; see Fig. 34A, 36A and 41B) having a first surface, first connection pads (Fig. 34A; par. 651, 658, 659) on the first surface (bottom), and a second surface (top) opposite to the first surface (bottom); a first connection member (upper 101) on the first surface (bottom) of at least one of the plurality of first semiconductor chips (100 of upper 301) and having a first redistribution layer (upper 27) electrically connected to the first connection pads (see Fig. 34A and 41B); a plurality of second semiconductor chips (100 of lower 301; see Fig. 36A and par. 724; “may include two first type of chip packages 301, each of which may have the similar structure to that as illustrated in FIG. 36A, stacked with each other, i.e., top and bottom ones, and an non-volatile-memory (NVM) chip package 336 stacked on the bottom one of its first type of chip packages 301. For an element indicated by the same reference number shown in FIGS. 36A and 41A, the specification of the element as seen in FIG. 41A may be referred to that of the element as illustrated in FIG. 36A.” and par. 726; “the bottom one of its first type of chip packages 301 may include one or more first type of semiconductor chips 100 used for logic integrated-circuit (IC) chips 326, such as FPGA IC chip, graphic-processing unit (GPU) chip, central-processing-unit (CPU) chip or digital-signal-processing (DSP) chip”) having a third surface (bottom) and second connection pads on the third surface (see Fig. 34A); a second connection member (lower 101) on the third surface (bottom) of at least one of the plurality of second semiconductor chips (100 of lower 301) and having a second redistribution layer (lower 27) electrically connected to the second connection pads (see Fig. 34A); a plurality of vertical interconnectors (158) on the second connection member, at least partially around the plurality of second semiconductor chips (100 of lower 301; see also Fig. 36A), and electrically connecting the first redistribution layer (upper 27) to the second redistribution layer (lower 27); a mold portion (92/257) on the second connection member (lower 101), at least partially surrounding the plurality of second semiconductor chips (100 of lower 301) and the plurality of vertical interconnectors (158), and extending on the first connection member (upper 101) and side surfaces of the plurality of first semiconductor chips (100 of upper 301); and a scribe lane (indicated by arrow in the figure below) between ones of the plurality of first semiconductor chips (100 of upper 301).
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Referring to Claim 16, Lin further teaches wherein the ones of the plurality of first semiconductor chips (100 of upper 301) are at opposing sides of the scribe lane and are integrally connected (via upper 101 and 564) on a same plane.
Referring to Claim 17, Lin further teaches wherein a distance between the ones of the plurality of first semiconductor chips (100 of upper 301) is different from a distance between ones of the plurality of second semiconductor chips (100 of lower 301).
Allowable Subject Matter
Claims 19 and 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 3 and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As insofar as Claim 3 is definite, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor package wherein a height from the upper surface of the base substrate to the second inactive surface of the upper semiconductor chip is less than a height from the upper surface of the base substrate to an upper surface of the second portion of the mold portion in combination with all of the limitations of Claims 1 and 3.
Regarding Claim 18, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor package wherein a height from an upper surface of the second connection member to the second surface of the at least one of the plurality of first semiconductor chips is less than a height from the upper surface of the second connection member to an uppermost surface of the mold portion in combination with all of the limitations of Claim 15 and 18.
As insofar as Claim 19 is definite, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor package wherein the plurality of upper semiconductor chips have a greater area than the plurality of lower semiconductor chips; and wherein a height from an upper surface of the base substrate to an uppermost surface of the mold portion is greater than a height from the upper surface of the base substrate to the second inactive surface of the at least one of the plurality of upper semiconductor chips in combination with all of the limitations of Claim 19.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
Prosecution Insights