DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, and 11-15 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Jairazbhoy et al. (U.S. Patent 6,303,872) cited in the record.
As to claim 1, Jairazbhoy discloses a control board (an electronic assembly) that operates in a low-temperature environment having an absolute temperature of 77 K or lower, the control board (the assembly) as shown in figure 4 comprising:
a surface-mounted electronic component (30) having an electrode (40) formed on a bottom surface (46) thereof;
a wiring board (10) having a wiring pattern (not shown, but the PCB substrate 10 inherently having wiring patterns formed in/on the surface of the substrate 10) and a pad (20) formed on a front surface thereof, the pad (20) connecting the electrode (40) of the electronic component (30); and
a solder bonding portion (50) disposed on the pad (20), the solder bonding portion containing Sn as a main component (the solder-paste 20 contains at least 80%-90% of lead Sn) and soldering the pad and the electrode,
wherein the solder bonding portion (50) covers an outer corner portion of the
electrode (top portion 42, figure 4) on a side (44) close to the wiring board (10) and an entire surface adjacent to the outer corner portion (42, 44), and covers (by the profile 60) a corner portion of the pad (20) on a side close to the electronic component (30) and an entire surface adjacent to the corner portion, and
wherein an inner corner portion of the pad (not label, see figure 4) on the wiring board is shifted to be located outside a lower inner corner portion (49) of the corresponding electrode (46) on the electronic component when viewed from a center of the electronic component (30).
As to claim 2, Jairazbhoy discloses after the pad (20) is soldered, the electronic component (30) is covered with solder up to an upper outer corner portion (48) of the electrode (42) which is far from the wiring board (10).
As to claim 3, Jairazbhoy discloses the electronic component (the SMD 30 is common be a passive component, which is either of a resistor or capacitor) is a chip resistor or a chip capacitor including two of the electrodes (40).
As to claim 4, Jairazbhoy discloses an outer corner portion of the pad (20-figure 4) on the wiring board (10) is shifted to be located outside a lower outer corner portion (46) of the corresponding electrode on the electronic component (30) when viewed from the center of the electronic component.
As to claim 5, Jairazbhoy discloses in figure 4 a first shift amount to outside of the inner corner portion of the pad (20) is less than a second shift amount to outside of the outer corner portion of the pad.
As to claim 7, Jairazbhoy discloses the soldering (50, 60) is performed by BGA bonding or QFN bonding, and the outer corner portion (49) of the electrode (40) on the electronic component (30) to be mounted on the side close to the wiring board (10) and the entire surface adjacent to the outer corner portion (42, 44) are covered with solder, and the corner portion of the pad (20) on the side close to the electronic component (30) and the entire surface adjacent to the corner portion are covered with solder.
As to claim 14, Jairazbhoy discloses the solder bonding portion (60) covers upper inside and outside corners of the pad (20).
As to claim 15, Jairazbhoy discloses a gap (beta 2 closed to the F2) between the lower inner corner portion (49) of the electrode and the wiring board (10) is devoid of the solder bonding portion.
As to claim 11, Jairazbhoy discloses a method for manufacturing a control board (the electronic circuit assembly) in which an electronic component (30) having a plurality of electrodes (40) formed on a bottom corner portion (46) thereof is connected to, by a solder material (50, 60), a wiring board (10) having a wiring pattern (not shown, but the PCB substrate 10 inherently having wiring patterns formed in/on the surface of the substrate 10 for electrical connected and routed the components) and pads (20) formed on a front surface thereof, the pads (20) connecting the electrodes (40) of the electronic component, as shown in figure 4 the method comprising:
disposing a center position of the pad (20) on the control board to be located
outside a center position of the electrode (40) to be bonded with respect to a center
position of the electronic component;
performing soldering (50, 60) of the electrode (40) and the pad (20) by disposing a solder material containing Sn as a main component (the solder-paste 20 contains at least 80%-90% of lead Sn) on the pad (20), disposing the electrode (40) of the electronic component on the solder material (50, 60), and performing heating and
melting; and
performing soldering by adjusting an amount of the solder material (50, 60) such that after the soldering, a corner portion (48, 49) of the electrode on a side close to the wiring board (10) and an entire lower surface adjacent to the corner portion are covered with the solder material, and a corner portion of the pad (20) on a side close to the electronic component (30) and an entire upper surface adjacent to the corner portion are covered with the solder material (60),
wherein an inner corner portion of the pad (not label, see figure 4) on the wiring board is shifted to be located outside a lower inner corner portion (49) of the corresponding electrode (46) on the electronic component when viewed from a center of the electronic component (30).
As to claim 12, Jairazbhoy discloses the electrodes (40) each have an entire short-side side surface (44) of the electronic component, a lower surface (46) extending from the short-side side surface to a part of a bottom surface, and an upper surface (42) extending from the short-side side surface (44) to a part of a front surface, and during the soldering (50, 60), solder (60) is formed such that an upper corner portion of the electrode which is far from the wiring board is covered with solder.
As to claim 13, Jairazbhoy discloses the electronic component (the SMD 30 is common be a passive component, which is either of a resistor or capacitor) is a chip resistor including two of the electrodes (40), and the wiring board (10) is manufactured such that an inner corner portion of the pad (20) on the wiring board (10) is shifted to be located outside a lower inner corner portion (49) of the corresponding electrode (40) on the electronic component (30) when viewed from a center of the electronic component, and an outer corner portion of the pad on the wiring board is shifted to be located outside a lower outer corner portion (49) of the corresponding electrode on the electronic component when viewed from the center of the electronic component (30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jairazbhoy in view of Tsuboi (‘616).
Regarding claim 6, Jairazbhoy discloses all of the limitations of claimed invention except for the limitations of claim 6.
Tsuboi discloses a plurality of the electronic components (1A, 1B) are mounted on the wiring board (5), a plurality of the flat plate-shaped electrodes (3, 4) are formed on bottom surfaces of the electronic components,
a plurality of flat plate-shaped pads (7, 8) corresponding to the electrodes are
formed on the wiring board,
an entire configuration is heated and melted (column 7, line 6+) in a state in
which a solder material (9) is sandwiched between the electrodes and the pads, and
soldering is performed such that lower corner portions of the electrodes on all the
electronic components (1A, 1B) and entire surfaces adjacent to the lower corner
portions, and upper corner portions of all the pads and entire surfaces adjacent to the
upper corner portions are covered with solder.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Tsuboi employed in the control board of Jairazbhoy in order to manage electrical signals, powers, and data characteristic.
As to claim 8, Jairazbhoy discloses a control board (the electronic circuit assembly) that operates in a low-temperature environment having an absolute temperature of 77 K or lower, as shown in figure 4 comprising:
[[a plurality of surface-mounted electronic components]] a SMD component (30) having a plurality of electrodes (40) formed on bottom surfaces (46) thereof which are connected to, by a solder material (50, 60), a wiring board having (10) a wiring pattern (not shown, but the PCB substrate 10 inherently having wiring patterns formed in/on the surface of the substrate 10 for electrical connected and routed the components) and pads (20) formed on a front surface thereof, the pads connecting the electrodes of the electronic components,
wherein the plurality of electrodes (40) are disposed in inner portions of the bottom surfaces of the electronic component (30) that are not in contact with edge portions, and
wherein in a state after soldering (50, 60), corner portions of the electrodes on a side close to the wiring board (10) and entire lower surfaces adjacent to the corner portions are covered with solder (60), and corner portions of the pads (20) on a side close to the electronic component (30) and entire upper surfaces adjacent to the corner portions are covered with solder, and
wherein an inner corner portion of the pad (not label, see figure 4) on the wiring board is shifted to be located outside a lower inner corner portion (49) of the corresponding electrode (46) on the electronic component when viewed from a center of the electronic component (30).
Jairazbhoy does not disclose the control board having a plurality of the electronic components.
Tsuboi discloses a plurality of the electronic components (1A, 1B) are mounted on the wiring board (5).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Tsuboi employed in the control board of Jairazbhoy in order to manage electrical signals, powers, and data characteristic.
Regarding to claim 9, Jairazbhoy as modified by Tsuboi teaches area sizes of lower surfaces of the plurality of electrodes (3, 4) are larger than area sizes of upper surfaces of the pads (7, 8) facing the plurality of electrodes (3, 4).
Regarding to claim 10, Jairazbhoy as modified by Tsuboi discloses the electronic components (1A, 1B) are chip resistors or chip capacitors, column 1, lines 19+.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T DINH/Primary Examiner, Art Unit 2848