Prosecution Insights
Last updated: July 17, 2026
Application No. 18/633,698

CONTROL BOARD AND METHOD FOR MANUFACTURING SAME

Non-Final OA §103
Filed
Apr 12, 2024
Priority
Aug 25, 2023 — JP 2023-137346
Examiner
DINH, TUAN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Ltd.
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
930 granted / 1181 resolved
+10.7% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
30 currently pending
Career history
1221
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
65.0%
+25.0% vs TC avg
§102
17.5%
-22.5% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1181 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/16/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jairazbhoy et al. (‘872) in view of Naruse et al. (U.S. Patent 5,838,070). Regarding to claim 1, Jairazbhoy discloses a control board (an electronic assembly) that operates in a low-temperature environment having an absolute temperature of 77 K or lower, the control board (the assembly) as shown in figure 4 comprising: a surface-mounted electronic component (30) having an electrode (40) formed on a bottom surface (46) thereof; a wiring board (10) having a wiring pattern (not shown, but the PCB substrate 10 inherently having wiring patterns formed in/on the surface of the substrate 10) and a pad (20) formed on a front surface thereof, the pad (20) connecting the electrode (40) of the electronic component (30); and a solder bonding portion (50) disposed on the pad (20), the solder bonding portion containing Sn as a main component (the solder-paste 20 contains at least 80%- 90% of lead Sn) and soldering the pad and the electrode, wherein the solder bonding portion (50) covers an outer corner portion of the electrode (top portion 42, figure 4) on a side (44) close to the wiring board (10) and an entire surface adjacent to the outer corner portion (42, 44), and covers (by the profile 60) a corner portion of the pad (20) on a side close to the electronic component (30) and an entire surface adjacent to the corner portion. Jairazbhoy does not specifically disclose an inner corner portion of the pad on the wiring board is disposed outside a lower inner corner portion of the corresponding electrode on the electronic component when viewed from a center of the electronic component. Naruse teaches an electronic circuit apparatus as shown in figures 1-4 comprising an inner corner portion (22 or 23) of the pad (8 or 9) on the wiring board (1) is disposed outside a lower inner corner portion of the corresponding electrode (4 or 5) on the electronic component (chip capacitor 2) when viewed from a center of the electronic component (2). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Naruse employed in the control board of Jairazbhoy in order to provide excellent bonding and prevent cracking structure. As to claim 2, Jairazbhoy as modified by Naruse discloses after the pad (20) is soldered, the electronic component (30) is covered with solder up to an upper outer corner portion (48) of the electrode (42) which is far from the wiring board (10). As to claim 3, Jairazbhoy as modified by Naruse discloses the electronic component (the SMD 30 is common be a passive component, which is either of a resistor or capacitor) is a chip resistor or a chip capacitor including two of the electrodes (40). As to claim 4, Jairazbhoy as modified by Naruse discloses an outer corner portion of the pad (20-figure 4) on the wiring board (10) is shifted to be located outside a lower outer corner portion (46) of the corresponding electrode on the electronic component (30) when viewed from the center of the electronic component. As to claim 5, Jairazbhoy as modified by Naruse discloses in figure 4 a first shift amount to outside of the inner corner portion of the pad (20) is less than a second shift amount to outside of the outer corner portion of the pad. Regarding claim 6, as modified by Naruse teaches a plurality of the electronic components (2, 3) are mounted on the wiring board (1), a plurality of the flat plate-shaped electrodes (8-11) are formed on bottom surfaces of the electronic components, a plurality of flat plate-shaped pads (4-7) corresponding to the electrodes (8-11) are formed on the wiring board (1), an entire configuration is heated and melted (column 4, line 57+) in a state in which a solder material is sandwiched between the electrodes (8-11) and the pads (4-7), and soldering is performed such that lower corner portions of the electrodes on all the electronic components (2, 3) and entire surfaces adjacent to the lower corner portions, and upper corner portions of all the pads and entire surfaces adjacent to the upper corner portions are covered with solder. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Naruse employed in the control board of Jairazbhoy in order to manage electrical signals, powers, and data characteristic. As to claim 7, Jairazbhoy as modified by Naruse discloses the soldering (50, 60) is performed by BGA bonding or QFN bonding, and the outer corner portion (49) of the electrode (40) on the electronic component (30) to be mounted on the side close to the wiring board (10) and the entire surface adjacent to the outer corner portion (42, 44) are covered with solder, and the corner portion of the pad (20) on the side close to the electronic component (30) and the entire surface adjacent to the corner portion are covered with solder. As to claim 14, Jairazbhoy as modified by Naruse discloses the solder bonding portion (60) covers upper inside and outside corners of the pad (20). As to claim 15, Jairazbhoy as modified by Naruse discloses a gap (beta 2 closed to the F2) between the lower inner corner portion (49) of the electrode and the wiring board (10) is devoid of the solder bonding portion. As to claim 8, Jairazbhoy discloses a control board (the electronic circuit assembly) that operates in a low-temperature environment having an absolute temperature of 77 K or lower, as shown in figure 4 comprising: [[a plurality of surface-mounted electronic components]] a SMD component (30) having a plurality of electrodes (40) formed on bottom surfaces (46) thereof which are connected to, by a solder material (50, 60), a wiring board having (10) a wiring pattern (not shown, but the PCB substrate 10 inherently having wiring patterns formed in/on the surface of the substrate 10 for electrical connected and routed the components) and pads (20) formed on a front surface thereof, the pads connecting the electrodes of the electronic components, wherein the plurality of electrodes (40) are disposed in inner portions of the bottom surfaces of the electronic component (30) that are not in contact with edge portions, and wherein in a state after soldering (50, 60), corner portions of the electrodes on a side close to the wiring board (10) and entire lower surfaces adjacent to the corner portions are covered with solder (60), and corner portions of the pads (20) on a side close to the electronic component (30) and entire upper surfaces adjacent to the corner portions are covered with solder. Jairazbhoy does not disclose the control board having a plurality of the electronic components, and further Jairazbhoy does not specifically disclose an inner corner portion of the pad on the wiring board is disposed outside a lower inner corner portion of the corresponding electrode on the electronic component when viewed from a center of the electronic component. Naruse teaches an electronic circuit apparatus as shown in figures 1-4 comprising the control board having a plurality of the electronic components (2, 3), and an inner corner portion (22 or 23) of the pad (8 or 9) on the wiring board (1) is disposed outside a lower inner corner portion of the corresponding electrode (4 or 5) on the electronic component (chip capacitor 2) when viewed from a center of the electronic component (2). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Naruse employed in the control board of Jairazbhoy in order to provide excellent bonding and prevent cracking structure. Regarding to claim 9, Jairazbhoy as modified by Naruse teaches area sizes of lower surfaces of the plurality of electrodes (4-7) are larger than area sizes of upper surfaces of the pads (8-11) facing the plurality of electrodes (3, 4). Regarding to claim 10, Jairazbhoy as modified by Naruse teaches the electronic components (2, 3) are chip resistors or chip capacitors. As to claim 11, Jairazbhoy discloses a method for manufacturing a control board (the electronic circuit assembly) in which an electronic component (30) having a plurality of electrodes (40) formed on a bottom corner portion (46) thereof is connected to, by a solder material (50, 60), a wiring board (10) having a wiring pattern (not shown, but the PCB substrate 10 inherently having wiring patterns formed in/on the surface of the substrate 10 for electrical connected and routed the components) and pads (20) formed on a front surface thereof, the pads (20) connecting the electrodes (40) of the electronic component, as shown in figure 4 the method comprising: disposing a center position of the pad (20) on the control board to be located outside a center position of the electrode (40) to be bonded with respect to a center position of the electronic component; performing soldering (50, 60) of the electrode (40) and the pad (20) by disposing a solder material containing Sn as a main component (the solder-paste 20 contains at least 80%-90% of lead Sn) on the pad (20), disposing the electrode (40) of the electronic component on the solder material (50, 60), and performing heating and melting; and performing soldering by adjusting an amount of the solder material (50, 60) such that after the soldering, a corner portion (48, 49) of the electrode on a side close to the wiring board (10) and an entire lower surface adjacent to the corner portion are covered with the solder material, and a corner portion of the pad (20) on a side close to the electronic component (30) and an entire upper surface adjacent to the corner portion are covered with the solder material (60). Jairazbhoy does not specifically disclose an inner corner portion of the pad on the wiring board is disposed outside a lower inner corner portion of the corresponding electrode on the electronic component when viewed from a center of the electronic component. Naruse teaches an electronic circuit apparatus as shown in figures 1-4 comprising an inner corner portion (22 or 23) of the pad (8 or 9) on the wiring board (1) is disposed outside a lower inner corner portion of the corresponding electrode (4 or 5) on the electronic component (chip capacitor 2) when viewed from a center of the electronic component (2). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Naruse employed in the control board of Jairazbhoy in order to provide excellent bonding and prevent cracking structure. As to claim 12, Jairazbhoy as modified by Naruse discloses the electrodes (40) each have an entire short-side side surface (44) of the electronic component, a lower surface (46) extending from the short-side side surface to a part of a bottom surface, and an upper surface (42) extending from the short-side side surface (44) to a part of a front surface, and during the soldering (50, 60), solder (60) is formed such that an upper corner portion of the electrode which is far from the wiring board is covered with solder. As to claim 13, Jairazbhoy as modified by Naruse discloses the electronic component (the SMD 30 is common be a passive component, which is either of a resistor or capacitor) is a chip resistor including two of the electrodes (40), and the wiring board (10) is manufactured such that an inner corner portion of the pad (20) on the wiring board (10) is shifted to be located outside a lower inner corner portion (49) of the corresponding electrode (40) on the electronic component (30) when viewed from a center of the electronic component, and an outer corner portion of the pad on the wiring board is shifted to be located outside a lower outer corner portion (49) of the corresponding electrode on the electronic component when viewed from the center of the electronic component (30). Response to Arguments Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Show 2 earlier events
Feb 04, 2026
Response Filed
Mar 02, 2026
Final Rejection mailed — §103
Apr 16, 2026
Request for Continued Examination
Apr 21, 2026
Interview Requested
Apr 23, 2026
Response after Non-Final Action
May 05, 2026
Applicant Interview (Telephonic)
May 05, 2026
Examiner Interview Summary
May 12, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.3%)
2y 11m (~7m remaining)
Median Time to Grant
High
PTA Risk
Based on 1181 resolved cases by this examiner. Grant probability derived from career allowance rate.

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