DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 27 July 2026 is acknowledged.
Claim Objections
Claims 16, 17, 19, and 20 are objected to because of the following informalities:
In claim 16, line 2, the word “comprise” appears it should be –comprises--, because the noun is singular.
In claim 17, line 2, the word “comprise” appears it should be –comprises--, because the noun is singular.
In claim 17, line 6, the phrase “second side respect to” appears it should be --second side with respect to--.
In claim 19, line 15, the word “comprise” appears it should be –comprises--, because the noun is singular.
In claim 19, Lines 17, 20, and 23, the phrase “extend in” appears it should be –extending at—.
In claim 20, line 4, the phrase “extend from” appears it should be –extending from—.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 5 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed had possession of the claimed invention. The specification contains no substantiation of the limitations in claim 5 regarding height. Notably, it appears the height of the first bonding pad 1173 shown in Fig. 1D is intentionally higher than the second bonding pad 1177 or tracer pattern 1175. The nearest teaching in the specification to the height of the three structures mentioned in claim 5 describes only a vertical level.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2, 16, and 19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “a vertex of the semiconductor chip” in claims 2, 16, and 19 is used without clear meaning, while the accepted meaning is “peak.” The term is indefinite because the specification does not clearly redefine the term. The only mention of “vertex” in the specification is in paragraph [0007], without a feature on a chip clearly identified as described by that term. For the purpose of examination, the term “vertex” will be ignored.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, 11-13, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220199561 A1, hereinafter “Kim”), in view of Bishop et al (WO 2013169801 A1, hereinafter “Bishop”).
Regarding Claim 1 – Kim discloses a semiconductor package comprising: a package substrate (1100 [0076]); a redistribution structure (1210 [0076]) comprising: an insulating layer provided on a first side of the package substrate (1210 may include insulating material [0076]); external connection terminals provided on a first side of the redistribution structure (1240 [0077]); and a semiconductor chip provided on the redistribution structure (combination of 1400 and 1402 [0076]), the semiconductor chip comprising a chip body (1400 [0076] and Fig. 17) and chip connection terminals provided on a first side of the chip body (1402 [0076] and Fig. 17).
Kim fails to disclose a plurality of horizontal redistribution structures provided in the insulating layer and arranged adjacent to each other in a first horizontal direction and a second horizontal direction, the first and the second horizontal directions parallel to an upper surface of the package substrate and the second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of horizontal redistribution structures comprises: a via through the insulating layer; a tracer pattern formed integrally with the via and extending at an angle from the first horizontal direction and the second horizontal direction; a first bonding pad provided on the insulating layer, integrally formed with the via, and formed at a first position on the tracer pattern; and a second bonding pad formed at a second position on the tracer pattern different from the first position and bonded to the chip connection terminal.
However, Bishop discloses a plurality of horizontal redistribution structures provided in the insulating layer and arranged adjacent to each other in a first horizontal direction and a second horizontal direction (combination of 205, 212, 214, 216, and 219 in Bishop [0026-0027], arranged on the X-Y plane, as shown in Figs. 2C and 3), the first and the second horizontal directions parallel to an upper surface of the package substrate and the second horizontal direction perpendicular to the first horizontal direction (X-direction and Y-direction perpendicular, as shown in annotated Bishop Fig. 3), wherein each of the plurality of horizontal redistribution structures comprises: a via through the insulating layer (216/116, Bishop [0027] and Figs. 2C and 3); a tracer pattern formed integrally with the via and extending at an angle from the first horizontal direction and the second horizontal direction (214/114, Bishop [214] and Figs. 2C and 3); a first bonding pad provided on the insulating layer, integrally formed with the via, and formed at a first position on the tracer pattern (219/119, Bishop [0027] and Figs. 2C and 3); and a second bonding pad formed at a second position on the tracer pattern different from the first position and bonded to the chip connection terminal (118, Bishop [0029] and Fig. 3).
Bishop discloses a chip-scale package with a redistribution layer analogous to Kim. Bishop teaches placing horizontal redistribution structures between chip bonding pads and bump connectors for the benefit of connecting a ball grid array to the chip in a typical fan-out wafer level package (Bishop [0003]). The described construction is common in the semiconductor industry. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim and Bishop by placing horizontal redistribution structures between chip bonding pads and bump connectors for the benefit of connecting a ball grid array to the chip in a fan-out wafer level package.
PNG
media_image1.png
568
880
media_image1.png
Greyscale
PNG
media_image2.png
279
469
media_image2.png
Greyscale
PNG
media_image3.png
522
572
media_image3.png
Greyscale
Regarding Claim 2 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop further discloses the plurality of horizontal redistribution structures comprises: a first horizontal redistribution structure overlapping the semiconductor chip in a plan view (HDS1 overlapping 152, annotated Bishop Fig. 3), and a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction (HDS2 overlapping 152, annotated Bishop Fig. 3), wherein the first horizontal redistribution structure and the second horizontal redistribution structure are arranged on a first side with respect to a centerline crossing the center of the semiconductor package in the second horizontal direction (Centerline away from both in Y-direction, as shown in annotated Bishop Fig. 3).
Regarding Claim 3 – Kim modified by Bishop discloses all the limitations of claim 2.
The combination of Kim and Bishop further discloses a first angle at which the first horizontal redistribution structure extends with respect to the second horizontal direction is different from a second angle at which the second horizontal redistribution structure with respect to the second horizontal direction (a1 ≠ a2, as shown in annotated Bishop Fig. 3).
Regarding Claim 4 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop further discloses the first bonding pad does not overlap the semiconductor chip in a vertical direction (119 does not overlap 152, Bishop Fig. 3), and wherein the second bonding pad completely overlaps the semiconductor chip in the vertical direction (118 completely overlaps 152, Bishop Fig. 3).
Regarding Claim 7 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop further discloses the first bonding pad is positioned farther from the center of the semiconductor chip than the second bonding pad (119 farther from center of 152 than 118, Bishop Fig. 3).
Regarding Claim 8 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop further discloses the first bonding pad is positioned closer to the center of the semiconductor chip than the second bonding pad (119 closer to center of 152 than 118, Bishop Fig. 4).
PNG
media_image4.png
755
604
media_image4.png
Greyscale
Regarding Claim 11 – Kim discloses a semiconductor package comprising: a package substrate (1100 [0076]); a redistribution structure comprising: an insulating layer provided on a first side of the package substrate (1210 may include insulating material [0076]); a plurality of vertical redistribution structures (combination of 110, 120, and 122, Kim [0019-0021] and Fig. 1); external connection terminals provided on a first side of the redistribution structure (1240 [0077]); a first semiconductor chip provided on the redistribution structure (combination of 1400 and 1402 [0090]), the semiconductor chip comprising a first chip body (1400 [0090] and Fig. 17) and first chip connection terminals provided on a first side of the first chip body (1402 [0090] and Fig. 17); and a second semiconductor chip spaced apart from the first semiconductor chip in the first horizontal direction and comprising a second chip body and second chip connection terminals provided on a first side of the second chip body (1310 [0080-0082] and Fig. 17), wherein the plurality of vertical redistribution structures completely overlap the first semiconductor chip in a vertical direction (Kim [0046] and Fig. 8).
Kim fails to disclose a plurality of horizontal redistribution structures provided in the insulating layer and arranged adjacent to each other in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of horizontal redistribution structures comprises: a via through the insulating layer; a tracer pattern formed integrally with the via and extending at an angle from the first horizontal direction and the second horizontal direction; a first bonding pad provided on the insulating layer, integrally formed with the via, and formed at a first position on the tracer pattern; and a second bonding pad formed at a second position on the tracer pattern different from the first position and bonded to the second chip connection terminal.
However, Bishop discloses a plurality of horizontal redistribution structures provided in the insulating layer and arranged adjacent to each other (combination of 205, 212, 214, 216, and 219 in Bishop [0026-0027], arranged on the X-Y plane, as shown in Figs. 2C and 3) in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction (X-direction and Y-direction perpendicular, as shown in annotated Bishop Fig. 3), wherein each of the plurality of horizontal redistribution structures comprises: a via through the insulating layer (216/116, Bishop [0027] and Figs. 2C and 3); a tracer pattern formed integrally with the via and extending at an angle from the first horizontal direction and the second horizontal direction (214/114, Bishop [214] and Figs. 2C and 3); a first bonding pad provided on the insulating layer, integrally formed with the via, and formed at a first position on the tracer pattern (219/119, Bishop [0027] and Figs. 2C and 3); and a second bonding pad formed at a second position on the tracer pattern different from the first position and bonded to the second chip connection terminal (118, Bishop [0029] and Fig. 3).
Bishop discloses a chip-scale package with a redistribution layer analogous to Kim. Bishop teaches placing horizontal redistribution structures between chip bonding pads and bump connectors for the benefit of connecting a ball grid array to the chip in a typical fan-out wafer level package (Bishop [0003]). The described construction is common in the semiconductor industry. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim and Bishop by placing horizontal redistribution structures between chip bonding pads and bump connectors for the benefit of connecting a ball grid array to the chip in a fan-out wafer level package.
PNG
media_image5.png
395
518
media_image5.png
Greyscale
PNG
media_image6.png
532
584
media_image6.png
Greyscale
Regarding Claim 12 – Kim modified by Bishop discloses all the limitations of claim 11.
The combination of Kim and Bishop further discloses the first semiconductor chip comprises a logic semiconductor chip (Kim [0090]), and wherein the second semiconductor chip comprises a high bandwidth memory (HBM) chip (Kim [0081]).
Regarding Claim 13 – Kim modified by Bishop discloses all the limitations of claim 11.
The combination of Kim and Bishop further discloses each of the plurality of vertical redistribution structures comprises: a vertical redistribution via through the insulating layer (110, Kim [0019] and Fig. 1); and a vertical redistribution pad integrally formed with an upper portion of the vertical redistribution via and bonded to the first chip connection terminal (120, Kim [0021] and Fig. 1.
Regarding Claim 16 – Kim modified by Bishop discloses all the limitations of claim 11.
The combination of Kim and Bishop further discloses the plurality of horizontal redistribution structures further comprise: a first horizontal redistribution structure overlapping the second semiconductor chip in a plan view (HDS1 overlapping 152, annotated Bishop Fig. 3); and a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction (HDS2 overlapping 152, annotated Bishop Fig. 3), wherein the first horizontal redistribution structure and the second horizontal redistribution structure are arranged on a first side with respect to a centerline crossing the center of the second semiconductor chip in the second horizontal direction (Centerline away from both in Y-direction, as shown in annotated Bishop Fig. 3), and an inclined angle of the first horizontal redistribution structure with respect to the second horizontal direction is different from an inclined angle of the second horizontal redistribution structure with respect to the second horizontal direction (a1≠ a2, as shown in annotated Bishop Fig. 3).
Regarding Claim 17 – Kim modified by Bishop discloses all the limitations of claim 16.
The combination of Kim and Bishop further discloses the plurality of horizontal redistribution structures further comprise: a third horizontal redistribution structure spaced from the first horizontal redistribution structure in the second horizontal direction (HDS3 in annotated Bishop Fig. 3), wherein the first horizontal redistribution structure and the third horizontal redistribution structure are arranged on a second side respect to a centerline crossing the center of the second semiconductor chip in the first horizontal direction (same side of centerline in X-direction, as shown in annotated Bishop Fig. 3), and the inclined angle of the first horizontal redistribution structure with respect to the second horizontal direction is different from an inclined angle of the third horizontal redistribution structure with respect to the second horizontal direction (a1 ≠ a3, as shown in annotated Bishop Fig. 3).
Regarding Claim 18 – Kim modified by Bishop discloses all the limitations of claim 11.
The combination of Kim and Bishop further discloses the first bonding pad does not overlap the semiconductor chip in a vertical direction (119 does not overlap 152, Bishop Fig. 3), and wherein the second bonding pad completely overlaps the semiconductor chip in the vertical direction (118 completely overlaps 152, Bishop Fig. 3).
Regarding Claim 19 – Kim discloses a semiconductor package comprising a package substrate (1100 [0076]); a redistribution structure comprising: an insulating layer provided on a first side the package substrate (1210 may include insulating material [0076]), and a plurality of vertical redistribution structures (combination of 110, 120, and 122, Kim [0019-0021] and Fig. 1); external connection terminals arranged below the redistribution structure (1240 [0077]); a first semiconductor chip provided on the redistribution structure (combination of 1400 and 1402 [0090]), the semiconductor chip comprising a first chip body (1400 [0090] and Fig. 17) and first chip connection terminals arranged on a first side of the first chip body (1402 [0090] and Fig. 17); and a second semiconductor chip spaced apart from the first semiconductor chip in the first horizontal direction and comprising a second chip body and second chip connection terminals arranged on a first side of the second chip body (1310 [0080-0082] and Fig. 17); wherein the plurality of vertical redistribution structures completely overlap the first semiconductor chip in a vertical direction (Kim [0046] and Fig. 8).
Kim fails to disclose a plurality of horizontal redistribution structures provided in the insulating layer and arranged side-by-side in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction, wherein the plurality of horizontal redistribution structures further comprise: a first horizontal redistribution structure overlapping the second semiconductor chip in a plan view and extend in a first angle with respect to the second horizontal direction; a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction and extend in a second angle different from the first angle with respect to the second horizontal direction; and a third horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the second horizontal direction and extend in a third angle different from the first angle with respect to the second horizontal direction.
However, Bishop discloses a plurality of horizontal redistribution structures provided in the insulating layer and arranged side-by-side in a first horizontal direction and in a second horizontal direction (combination of 205, 212, 214, 216, and 219 in Bishop [0026-0027], arranged on the X-Y plane, as shown in Figs. 2C and 3) perpendicular to the first horizontal direction (X-direction and Y-direction perpendicular, as shown in annotated Bishop Fig. 3), wherein the plurality of horizontal redistribution structures further comprises: a first horizontal redistribution structure overlapping the second semiconductor chip in a plan view (HDS1 overlapping 152, annotated Bishop Fig. 3) and extending at a first angle with respect to the second horizontal direction (a1, annotated Bishop Fig. 3); a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction (HDS2, annotated Bishop Fig. 3) and extending at a second angle different from the first angle with respect to the second horizontal direction (a2, annotated Bishop Fig. 3); and a third horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the second horizontal direction (HDS3, annotated Bishop Fig. 3) and extending at a third angle different from the first angle with respect to the second horizontal direction (a3, annotated Bishop Fig. 3).
Bishop discloses a chip-scale package with a redistribution layer analogous to Kim. Bishop teaches placing horizontal redistribution structures between chip bonding pads and bump connectors for the benefit of connecting a ball grid array to the chip in a typical fan-out wafer level package (Bishop [0003]). The described construction is common in the semiconductor industry. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim and Bishop by placing horizontal redistribution structures between chip bonding pads and bump connectors for the benefit of connecting a ball grid array to the chip in a fan-out wafer level package.
Regarding Claim 20 – Kim modified by Bishop discloses all the limitations of claim 19.
The combination of Kim and Bishop further discloses each of the plurality of horizontal redistribution structures comprises: a via through the insulating layer (216/116, Bishop [0027] and Figs. 2C and 3); a tracer pattern formed integrally with the via and extending at an angle from the first horizontal direction and the second horizontal direction (214/114, Bishop [214] and Figs. 2C and 3); a first bonding pad provided on the insulating layer, integrally formed with the via, and formed at a first position on the tracer pattern (219/119, Bishop [0027] and Figs. 2C and 3); and a second bonding pad formed at a second position of the tracer pattern and bonded to the second chip connection terminal (118, Bishop [0029] and Fig. 3).
Claims 6, 9, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220199561 A1, hereinafter “Kim”), in view of Bishop et al (WO 2013169801 A1, hereinafter “Bishop”), and further in view of the following arguments.
Regarding Claim 6 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop fails to disclose the plurality of horizontal redistribution structures are arranged symmetrically with respect to a centerline crossing the center of the semiconductor chip in the first horizontal direction and a centerline crossing the center of the semiconductor chip in the second horizontal direction. However, it is commonly known in the semiconductor industry that symmetry can be applied to the layout of chip and redistribution layer connection pads, leading directly to arranging horizontal redistribution structures symmetrically with respect to a centerline crossing the center of the semiconductor chip. This is a prima facia case of obviousness by routine optimization. See MPEP 2144.05(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider arranging the plurality of horizontal redistribution structures symmetrically with respect to a centerline crossing the center of the semiconductor chip in the first horizontal direction and a centerline crossing the center of the semiconductor chip in the second horizontal direction.
Regarding Claim 9 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop further discloses the second bonding pad has a circular column shape (118, Bishop Fig. 3).
The combination of Kim and Bishop fails to disclose a length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad.
However, bond pad layout and bonding pad length are independently controlled variables in semiconductor processing and layout. Thus, making a length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad is a prima facie case of obviousness by routine optimization. See MPEP 2144.05(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider making a length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad.
Regarding Claim 14 – Kim modified by Bishop discloses all the limitations of claim 13.
The combination of Kim and Bishop fails to disclose a first length of the second bonding pad in the vertical direction is longer than a second length of the vertical redistribution pad in the vertical direction.
However, when it is desired to set the sides of the two semiconductor chips opposite the bonding pads at the same level as shown in Fig. 6A, and the thicknesses of the two semiconductor chips are different, it is obvious the length of the second bonding pad and the length of the vertical redistribution pad must be made different, requiring routine optimization. See MPEP 2144.05(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider making a length of the second bonding pad in the vertical direction longer than a length of the vertical redistribution pad in the vertical direction.
Regarding Claim 15 – Kim modified by Bishop discloses all the limitations of claim 11.
The combination of Kim and Bishop further discloses the second bonding pad has a circular column shape (118, Bishop Fig. 3).
The combination of Kim and Bishop fails to disclose a length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad.
However, bond pad layout and bonding pad length are independently controlled variables in semiconductor processing and layout. Thus, making a length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad is a prima facie case of obviousness by routine optimization. See MPEP 2144.05(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider making a length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220199561 A1, hereinafter “Kim”), in view of Bishop et al (WO 2013169801 A1, hereinafter “Bishop”), and further in view of Arifeen (US 11,164,837 B1, hereinafter “Arifeen”).
Regarding Claim 10 – Kim modified by Bishop discloses all the limitations of claim 1.
The combination of Kim and Bishop fails to disclose the horizontal redistribution structure further comprises a third bonding pad formed on the tracer pattern between the first bonding pad and the second bonding pad, wherein the semiconductor chip further comprises a dummy chip connection terminal provided on a side of the chip body, and wherein the third bonding pad is bonded to the dummy chip connection terminal.
However, Arifeen discloses the semiconductor chip further comprises a dummy chip connection terminal provided on a side of the chip body, which could constitute a third bonding pad formed on the tracer pattern between the first bonding pad and the second bonding pad, wherein the third bonding pad is bonded to the dummy chip connection terminal (Arifeen column 2, lines 55-59, column 4, lines 29-36, and Fig. ).
Arifeen discloses a semiconductor chip-scale package analogous to Kim. Arifeen teaches some of the connection terminals can be dummy chip connection terminals for the benefit of structural support (Arifeen, column 1, lines 19-22). Such dummy chip connection terminals can easily be integrated in the vertical arrangement taught by Arifeen, or in an arrangement incorporating dummy chip connection terminals with the horizontal redistribution structures taught by Bishop. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim, Bishop, and Arifeen by incorporating dummy chip connection terminals for the benefit of structural support.
PNG
media_image7.png
335
551
media_image7.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights