DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to perfect the priority claim, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on 12 April 2024 and 31 August 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner except as otherwise indicated.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor device with conductive through-structures for backside power delivery.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-17 recites the limitation "the third conductive through-structure" in line 4 of claim 15 on page 6 , line 7 of claim 16 on page 7, and line 4 of claim 17 on page 7. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether applicant means to have “the third conductive through-structure” to mean “a third conductive through structure” or for claims 15-17 to be dependent on claim 14 instead of claim 13. For examination purposes, claims 15-17 will be examined as dependent on claim 14 instead of 13.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2022/0028895 A1, hereafter Kim) in view of Yu et al (US 2022/0302275 A1, hereafter Yu) and Wang et al (US 2024/0014283 A1, hereafter Wang).
Regarding claim 1, Kim discloses a semiconductor device (Fig. 1A 1) comprising:
a substrate (Fig. 1B laminate of 110+105; [0016]) including a first active region (Fig. 1A RX1; [0016]) and a second active region (Fig. 1A RX2; [0016]),
the first active region (RX1) and the second active region (RX2) extending in a first direction (Fig. 1A extend in Y direction; [0017]), the first active region (RX1) including a plurality of first active patterns (Fig. 1B FA on RX1; [0017]) spaced apart from each other by a first interval ([0017]), the second active region (RX2; [0017]) including a plurality of second active patterns (Fig. 1B FA on RX2),
a device isolation layer (Fig. 1B 112; [0021]) on the substrate (110), the device isolation layer (112) surrounding the first active region (RX1) and the second active region (RX2);
a gate structure (Figs. 1A, 1C GS) on the substrate (110), the gate structure (GS) extending in a second direction (Fig. 1A extend in X direction), the second direction intersecting the first direction (Fig. 1A; [0042]);
a first source/drain region (Fig. 1B 130 on RX1; [0029]) on the first active region (RX1) and a second source/drain region (Fig. 1B 130 on RX2; [0029]) on the second active region (RX2), the first source/drain region (on RX1) and the second source/drain region (130 on RX2) on opposite sides of the gate structure (GS), respectively ([0027]);
an interlayer insulating layer (Figs. 1B, 19D 128; [0028]) on the device isolation layer (112), the interlayer insulating layer (128) covering the gate structure (GS), the first source/drain region (130 on RX1), and the second source/drain region (130 on RX2);
a first contact structure (Fig. 1B CP1 on RX1; [0029]) and a second contact structure (CP1 on RX2) passing through (Fig. 1B) the interlayer insulating layer (128), the first contact structure (CP1 on RX1) and the second contact structure (CP1 on RX2) being connected ([0029]) to the first source/drain region (130 on RX1) and the second source/drain region (130 on RX2), respectively;
a first conductive through-structure (Fig. 1B VC+150; [0029]) electrically connected ([0029]) to the first contact structure (CP1), the first conductive through-structure (VC+150) passing through (Fig. 1B) the substrate (110) and the interlayer insulating layer (128);
a power delivery structure (Fig. 1B 160; [0033]) extending from a back surface of the substrate (Fig. 1B bottom of laminate of 110+105) toward a front surface of the substrate (Fig. 1B top of laminate of 110+105), the power delivery structure (160) in contact (Fig. 1B; [0033]) with a bottom surface of the first conductive through-structure (bottom of VC+150);
a backside interconnection structure (Fig. 1B 170+180; [0035]) on the back surface of the substrate (bottom of laminate of 110+105), the backside interconnection structure (170+180) including backside interconnection patterns (Fig. 1B 180), wherein
the first conductive through-structure (VC+150) is in contact (Fig. 1B) with a lower portion of the first contact structure (bottom surface of CP1),
the first conductive through-structure (VC+150) is electrically connected ([0029]) to the first source/drain region (130 of RX1) through the first contact structure (CP1).
Kim does not disclose the second active region including a plurality of second active patterns spaced apart from each other by a second interval,
the second interval being different from the first interval;
a second contact structure passing through the interlayer insulating layer, the second contact structure being connected to the second source/drain region;
a second conductive through-structure electrically connected to the second contact structure, respectively, the second conductive through-structure passing through the substrate and the interlayer insulating layer;
the power delivery structure in contact with a bottom surface of the second conductive through-structure;
a frontside interconnection structure on the front surface of the substrate, the frontside interconnection structure including frontside interconnection patterns; and
the second conductive through-structure is spaced apart from the second contact structure,
the second conductive through-structure is in contact with the frontside interconnection structure, and
the second conductive through-structure is electrically connected to the second source/drain region through the frontside interconnection structure.
Yu discloses active patterns (Fig. 4 112a-c [0033]; Fig. 35; [0087]-[0090]) spaced apart from each other by a second interval ([0033]; [0087]-[0090]), and the second interval being different from the first interval ([0033]; [0087]-[0090]). Yu is analogous to Kim in the art of field effect transistor (FET) structure.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to change the second interval to be different from the first interval in the device of Kim as demonstrated by Yu to adjust fin density via routine optimization for the desired device parameters.
Yu does not disclose a second contact structure passing through the interlayer insulating layer, the second contact structure being connected to the second source/drain region;
a second conductive through-structure electrically connected to the second contact structure, respectively, the second conductive through-structure passing through the substrate and the interlayer insulating layer;
the power delivery structure in contact with a bottom surface of the second conductive through-structure;
a frontside interconnection structure on the front surface of the substrate, the frontside interconnection structure including frontside interconnection patterns; and
the second conductive through-structure is spaced apart from the second contact structure,
the second conductive through-structure is in contact with the frontside interconnection structure, and
the second conductive through-structure is electrically connected to the second source/drain region through the frontside interconnection structure.
Wang discloses a second contact structure (Fig. 21A 730; [0051]; analogous to 130 in RX2 of Kim) passing through the interlayer insulating layer (Fig. 21A 323; [0051]; analogous to 128 of Kim), the second contact structure (730) being connected to the second source/drain region (Fig. 21A 321; [0051]; analogous to 130 of Kim);
a second conductive through-structure (Fig. 21A 720; [0050]-[0054]) electrically connected ([0052]) to the second contact structure (730), the second conductive through-structure (720) passing through the substrate (Fig. 21A 302; [0053]) and the interlayer insulating layer (323);
the power delivery structure (Fig. 21A 780; [0054]; analogous to 160 of Kim) in contact ([0054]) with a bottom surface of the second conductive through-structure (bottom of 720);
a frontside interconnection structure (Fig. 21A 750+760; [0052]) on the front surface of the substrate (top of 302), the frontside interconnection structure (750+760) including frontside interconnection patterns (Fig. 21A 760; [0052]); and
the second conductive through-structure (720) is spaced apart (Fig. 21A) from the second contact structure (730),
the second conductive through-structure (720) is in contact ([0052]) with the frontside interconnection structure (750+760), and
the second conductive through-structure (720) is electrically connected ([0052]) to the second source/drain region (730) through the frontside interconnection structure (750+760).
Wang is analogous to Kim and Yu in the art of field effect transistor (FET) structure.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add the frontside interconnection structure and second conductive through-structure of Wang to the device of Kim to provide improved device performance and power efficiency by increasing interconnect density.
Regarding claim 2¸ Kim, Yu, and Wang disclose the semiconductor device of claim 1, wherein a
level of an upper end of the first conductive through-structure (top of VC+150) is lower than (Fig. 1B) a level of an upper end of each of the first contact structure (top of CP1 of RX1) and the second contact structure (top of CP1 of RX2), and
a level of an upper end of the second conductive through-structure (720) is a same level as the level of the upper end of the first contact structure (top of CP1 in RX1) and the level of the upper end of the second contact structure (top of CP1 in RX2).
Through-structure 720 of Wang is in contact with interlayer insulating layer 750 (analogous to 128 of Kim) and at the same level as source/drain contact 730 (analogous to CP1 of Kim). Therefore, one skilled in the art would make the upper end of the second through-structure to be at the same level as the upper end of the first and second contact structures in Kim.
Regarding claim 4, Kim, Yu, and Wang disclose the semiconductor device of claim 1.
Kim, Yu, and Wang fail to explicitly disclose a level of a contact surface between the first conductive through-structure (Kim bottom of VC+150) and the power delivery structure (Kim 160) is lower than a level of a contact surface between the second conductive through-structure (Wang bottom of 720) and the power delivery structure (Wang 780, analogous to 160 of Kim).
However, Kim discloses adjusting the level of the contact surface between the through-structure and the power delivery structure (Figs. 20 and 21, 150 and 160; [0125]-[0129]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust to level of the contact surface to adjust power delivery between the power delivery structure and the through-structure to reach desired device performance.
Regarding claim 5, Kim, Yu, and Wang disclose the semiconductor device of claim 1.
Kim, Yu, and Wang fail to explicitly disclose each of the plurality of first active patterns has a first width, each of the plurality of second active patterns has a second width, and the second width is different from the first width.
However, Yu discloses active patterns having different widths ([0032]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to change the width of the active patterns in the second region to be different from width of the active patterns in the first region via routine optimization to modulate the power consumption and adjust fin density for the desired device parameters.
Regarding claim 6, Kim, Yu, and Wang disclose the semiconductor device of claim 1, comprising:
a plurality of channel layers (Yu Figs. 31, 32A 106; [0026]) on the first active region (Kim RX1) and the second active region (Kim RX2), the plurality of channel layers (106) being spaced apart (Yu Figs. 31, 32A) from each other in a vertical direction (Z direction), the vertical direction (Z direction) being perpendicular (Fig. 31) to an upper surface of the substrate (Yu Fig. 31 101), wherein
the gate structure (Kim Fig. 1C GS; Yu Fig. 32A 184+180; Yu [0039]) includes a gate electrode (Fig. 32A 184) and a gate dielectric layer (Fig. 32A 180),
the gate structure (Kim GS; Yu 184+180) extends in the second direction (Kim X direction) while surrounding each of the plurality of channel layers (Yu 106), and
the gate dielectric layer (Yu 180) is between the plurality of channel layers (Yu 106) and the gate electrode (Yu 184).
While Kim does not disclose a plurality of channel layers in the FinFET, Yu discloses the plurality of channels can be implemented in the device ([0016]). Therefore, one skilled in the art would replace the gate and fin structures of Kim with the gate and fin structures with channels of Yu to improve device performance.
8. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yu, and Wang as applied to claim 1 above, and further in view of Mahji et al (US 2023/0197612 A1, hereafter Mahji).
Regarding claim 3, Kim, Yu, and Wang disclose the semiconductor device of claim 1.
Kim, Yu, and Wang fail to disclose wherein a width of the first conductive through-structure in the second direction is greater than a width of the second conductive through-structure in the second direction.
Mahji discloses conductive through structures having a tapered shape (Fig. 1B; [0064]-[0066]). Mahji is analogous to Kim, Yu, and Wang in the art of semiconductor device structure and power delivery.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second conductive through-structures of in the device of Kim, Yu, and Wang to have different widths, with the width of the second through-structure being greater than the width of the first through-structure, to modulate signal and power delivery by modulating resistivity for the desired device performance.
9. Claim 7 and 9-10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yu, and Wang as applied to claim 1 above, and further in view of Chiang et al (US 2021/0305252 A1, hereafter Chiang).
Regarding claim 7, Kim, Yu, and Wang disclose the semiconductor device of claim 1.
Kim, Yu, and Wang fail to disclose a third source/drain region a third active region of the substrate; and
a third conductive through-structure extending from the back surface of the substrate toward the front surface of the substrate, wherein
the third active region includes a plurality of third active patterns spaced apart from each other by a third interval,
the third interval is less than the first interval and less than second interval,
the third source/drain region is on opposite sides of the gate structure,
the third conductive through-structure is connected to the third source/drain region and below the third source/drain region, and
the first interval is greater than the second interval.
Chiang discloses a third source/drain region (Fig. 19B 260; [0049]);
a third active region (Fig. 19B 208; [0049]) of the substrate (Fig. 19B 208; [0049]); and
a third conductive through-structure (Figs. 18D+19B 384; [0072]) extending from the back surface of the substrate (top of 208) toward the front surface of the substrate (bottom of 208), wherein
the third source/drain region (260) is on opposite sides (Fig. 19B) of the gate structure (Fig. 19B 240’; [0057]), and
the third conductive through-structure (384) is connected to the third source/drain region (208) and below the third source/drain region (through-structure 384 contacts source/drain 260 through backside).
Chiang is analogous to is analogous to Kim, Yu, and Wang in the art of FET structure.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Chiang with the device of Kim, Yu, and Wang to create a more power-efficient device to improve device performance. Additionally, one skilled in the art would find it reasonable to add the device of Chiang to the device of Kim to form a third region with the conformation claimed, as disclosed by Kim ([0130]).
Additionally, the device of Kim, Yu, Wang, and Chiang discloses the third active region (Chiang 19B 208) includes a plurality of third active patterns (Chiang 19B 208) spaced apart from each other by a third interval (Yu ([0033]; [0087]-[0090]);
the third interval is less than the first interval and less than second interval (Yu [0033]; [0087]-[0090]),
the first interval is greater than the second interval (Yu [0033]; [0087]-[0090]).
It would be obvious to one skilled in the art to change the interval of the active patterns to satisfy the claimed invention parameters via routine optimization to modulate fin density and achieve the desired device.
Regarding claim 9, Kim, Yu, Wang, and Chiang disclose the semiconductor device of claim 7, wherein
a level of an upper end of the third conductive through-structure (Chiang bottom of 384) is higher (Fig. 19B, where higher is interpreted to mean closer to frontside) than a level of a lower end of the third source/drain region (Chiang top of 260).
Regarding claim 10, Kim, Yu, Wang, and Chiang disclose the semiconductor device of claim 7.
Kim, Yu, Wang, and Chiang fail to explicitly disclose a level of an upper end of the first conductive through-structure (Kim top of VC+150) is lower than a level of an upper end of the second conductive through-structure (Wang 720), and
the level of the upper end of the first conductive through-structure (Kim top of VC+150) is higher than a level of an upper end of the third conductive through-structure (Chiang bottom of 384).
However, the upper surface of the second through-structure 720 of Wang is in contact with interlayer insulating layer 750 (analogous to 128 of Kim) and at the same level as the upper surface of source/drain contact 730 (analogous to CP1 of Kim) while the first through-structure VC+150 of Kim contacts the lower surface of the first contact structure (bottom of CP1 in RX1). Therefore, one skilled in the art would make the upper end of the second through-structure would be higher than the upper end of the first through-structure.
Additionally, the source/drain are at equal levels (Kim Fig. 1B and Wang Fig. 21A). Chiang discloses the upper surface of the third through-structure 384 to be below the fins 218 with channels 272 (Fig. 19B) while Kim discloses the upper surface of the first through-structure VC+150 to be above the fins FA (Fig. 1B). Therefore, one skilled in the art would make the level of the upper end of the first conductive through-structure higher than a level of an upper end of the third conductive through-structure.
10. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yu, Wang, and Chiang as applied to claim 7 above, and further in view of Mahji.
Regarding claim 8, Kim, Yu, Wang, and Chiang disclose the semiconductor device of claim 7.
Kim, Yu, Wang, and Chiang fail disclose the first conductive through-structure and the second conductive through-structure respectively have widths gradually increasing from the back surface of the substrate toward the front surface of the substrate, and
the third conductive through-structure has a width gradually decreasing from the back surface of the substrate toward the front surface of the substrate.
Mahji discloses conductive through structures having a tapered shape (Fig. 1B; [0064]-[0066]), tapering both towards and away (Figs. 1A+B) from the back surface of the substrate (102).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second conductive through-structures to gradually taper towards the back surface of the substrate and the third conductive through-structure to gradually taper towards the front surface of the substrate in the device of Kim, Yu, Wang, and Chiang to modulate signal and power delivery by modulating resistivity for the desired device performance.
11. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Wang.
Regarding claim 11, Kim discloses a semiconductor device (Figs. 1A+B 1) comprising:
a substrate (Fig. 1B laminate of 110+105; [0016]) having a first region (Fig. 1A RX1; [0016]) having a first pattern density (Fig. 1B FA on RX1; [0017]) and a second region (RX2; [0017]) having a second pattern density (Fig. 1B FA on RX2);
first elements (Fig. 1B 130 on RX1; [0029]) on the substrate (110) in the first region (RX1);
a first conductive through-structure (Fig. 1B VC+150; [0112]) passing through the substrate (110), the first conductive through-structure (VC+150) electrically connected to the first elements (130);
second elements (Fig. 1B 130 on RX2) on the substrate (110) in the second region (RX2);
a contact structure (Fig. 1B CP1 in RX1; [0029]) connected to at least one of each of the first elements (130 in RX1) in the first region (RX1) or each of the second elements (130 in RX2) in the second region (RX2);
a power delivery structure (Fig. 1B 160; [0033]) extending from a back surface of the substrate (bottom of laminate of 110+105) toward a front surface of the substrate (top of laminate of 110+105), the power delivery structure (160) in contact (Fig. 1B; [0033]) with a bottom surface of the first conductive through-structure (bottom of VC+150);
a backside interconnection structure (Fig. 1B 170+180; [0035]) including backside interconnection patterns (Fig. 1B 180; [0035]) adjacent to the back surface of the substrate (bottom of laminate of 110+105), the back surface of the substrate (bottom of laminate of 110+105) being opposite the front surface of the substrate (bottom of laminate of 110+105), wherein
the first conductive through-structure (VC+150) extends from the front surface of the substrate (top of laminate of 110+105) toward the back surface of the substrate (bottom of laminate of 110+105).
Kim does not disclose a second conductive through-structure passing through the substrate, the second conductive through-structure electrically connected to the second elements;
the power delivery structure in contact with a bottom surface of the first conductive through-structure and a bottom surface of the second conductive through-structure;
a frontside interconnection structure electrically connected to at least one of the first elements or the second elements on the front surface of the substrate, the frontside interconnection structure including frontside interconnection patterns in contact with an upper surface of the contact structure; and
a level of an upper end of the first conductive through-structure is different from a level of an upper end of the second conductive through-structure, and
at least one of the first conductive through-structure or the second conductive through-structure is spaced apart from the contact structure.
Through-structure 720 of Wang is in contact with interlayer insulating layer 750 (analogous to 128 of Kim) and at the same level as source/drain contact 730 (analogous to CP1 of Kim). Therefore, one skilled in the art would make the upper end of the second through-structure to be at the same level as the upper end of the first and second contact structures in Kim.
Wang discloses a second conductive through-structure (Fig. 21A 720; [0050]-[0054]) passing through the substrate (Fig. 21A 302), the second conductive through-structure (720) electrically connected ([0052]) to the second elements (Fig. 21A 321; [0051]; analogous to 130 of Kim);
the power delivery structure (Fig. 21A 780; [0054]; analogous to 160 of Kim) in contact ([0054]) with a bottom surface of the second conductive through-structure (bottom of 720);
a frontside interconnection structure (Fig. 21A 750+760; [0052]) electrically connected ([0052]) to the second elements (321) on the front surface of the substrate (top of 302), the frontside interconnection structure (750+760) including frontside interconnection patterns (Fig. 21A 760; [0052]) in contact with an upper surface of the contact structure (Fig. 21A 730; [0051]; analogous to 130 in RX1 of Kim); and
the second conductive through-structure (720) is spaced apart (Fig. 21A) from the contact structure (730).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add the frontside interconnection structure and second conductive through-structure of Wang to the device of Kim to provide improved device performance and power efficiency by increasing interconnect density.
Additionally, Kim and Wang fail to explicitly disclose a level of an upper end of the first conductive through-structure (Kim VC+150) is different from a level of an upper end of the second conductive through-structure (Wang 720).
However, the upper surface of the second through-structure 720 of Wang is in contact with interlayer insulating layer 750 (analogous to 128 of Kim) and at the same level as the upper surface of source/drain contact 730 (analogous to CP1 of Kim) while the first through-structure of contacts the lower surface of the first contact structure (bottom of CP1 in RX1). Therefore, one skilled in the art would make the upper ends of the conductive through-structures different from each other like the claimed invention.
Regarding claim 12, Kim and Wang disclose the semiconductor device of claim 11, wherein
the first conductive through-structure (Kim VC+150) is spaced apart (Fig. 1B) from the first elements (130 on RX1) and the first conductive through-structure (VC+150) is electrically connected ([0112]) to the first elements (130) through the contact structure (CP1), and
the second conductive through-structure (Wang 720) is spaced apart from the second elements (CP1 on RX2) and the second conductive through-structure (720) is electrically connected ([0052]) to the second elements (CP1 on RX2) through the frontside interconnection structure (760).
12. Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Wang as applied to claim 11 above, and further in view of Yu.
Regarding claim 13, Kim and Wang disclose the semiconductor device of claim 11.
Kim and Wang fail to disclose the second pattern density is higher than the first pattern density.
Yu discloses a second interval (i.e. distance between patterns) being different from a first interval ([0033]; [0087]-[0090]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to change the density of the second pattern (density can be interpreted to mean number of active patterns per distance) to be greater from the density of the first pattern via routine optimization, as disclosed by Yu, to achieve desired device performance and improve device performance.
13. Claim 14-17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Wang, and Yu as applied to claim 13 above, and further in view of Chiang.
Regarding claim 14, Kim, Wang, and Yu disclose the semiconductor device of claim 13.
Kim, Wang, and Yu fail to disclose a third conductive through-structure passing through the substrate; and
third elements on a third region of the substrate, wherein
the third region has a third pattern density,
the third pattern density is higher than the second pattern density, and
the third conductive through-structure is in contact with the third elements.
Chiang discloses a third conductive through-structure (Figs. 18D+19B 384; [0072]) passing through the substrate (Fig. 19B 208); and
third elements (Fig. 19B 260; [0049]) on a third region (Fig. 19B; [0049]) of the substrate (Fig. 19B 208; [0049]), wherein
the third conductive through-structure (384) is in contact (Fig. 19B) ([0072]) with the third elements (260).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Chiang with the device of Kim, Yu, and Wang to create a more power-efficient device to improve device performance. Additionally, one skilled in the art would find it reasonable to add the device of Chiang to the device of Kim to form a third region with the conformation claimed, as disclosed by Kim ([0130]).
Additionally, Kim, Wang, Yu, and Chiang fail to explicitly disclose the third region (Chiang Fig. 19B) has a third pattern density, and to disclose the third pattern density is higher than the second pattern density.
However, Yu discloses that an interval (and therefore density as explained in claim 13) between patterns in the third region can change ([0033]; [0087]-[0090]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious that the third pattern have a pattern density, and to change the third pattern density to be greater than the second pattern density via routine optimization to fit the desired device parameters and improve device performance.
Regarding claim 15, Kim, Wang, Yu, and Chiang disclose the semiconductor device of claim 13 (interpreted as claim 14), wherein
the first conductive through-structure (Kim VC+150) is in contact (Fig. 1B) with a lower portion of the contact structure (Kim CP1 in RX1), and
the second conductive through-structure (Wang 720) and the third conductive through-structure (Chiang 384) are spaced apart (Wang Fig. 21A, Chiang Fig. 19B) from the contact structure (CP1 in RX1).
Regarding claim 16, Kim, Wang, Yu, and Chiang disclose the semiconductor device of claim 13 (interpreted as claim 14), wherein
the level of the upper end of the second conductive through-structure (Wang 720) is a same level (Wang Fig. 21A) as a level of an upper end of the contact structure (Wang 730, analogous to CP1 in RX2 in Kim).
Kim, Wang, Yu, and Chiang fail to explicitly disclose the level of the upper end of the second conductive through-structure is higher than the level of the upper end of the first conductive through-structure, and
the level of the upper end of the first conductive through-structure is higher than a level of an upper end of the third conductive through-structure.
However, Wang discloses a level of an upper end of the second conductive through-structure (720) is a same level as the level of the upper end of the contact structure (top of CP1 in RX1), and Kim discloses that the upper end of the first conductive through-structure (VC+150) is in contact with the lower end of the contact (bottom of CP1 in RX1).
Additionally, the source/drain are at equal levels (Kim Fig. 1B and Wang Fig. 21A). Chiang discloses the upper surface of the third through-structure 384 to be below the fins 218 (Fig. 19B) while Kim discloses the upper surface of the first through-structure VC+150 to be above the fins FA (Fig. 1B). Therefore, one skilled in the art would make the level of the upper end of the first conductive through-structure higher than a level of an upper end of the third conductive through-structure.
Regarding claim 17, Kim and Wang disclose the semiconductor device of claim 13 (interpreted as claim 14), wherein
the first conductive through-structure (Kim VC+150) and the second conductive through-structure (Wang 720) extend from the front surface of the substrate (Kim top of 110+105) toward the back surface of the substrate (bottom of 110+105), and
the third conductive through-structure (Chiang 384) extends (Chiang Fig. 19B) from the back surface of the substrate (Chiang top of 208) toward the front surface of the substrate (bottom of 208).
14. Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chiang, Yu, and Wang.
Regarding claim 18¸ Kim discloses a semiconductor device (Fig. 1A+B 1) comprising:
a substrate (Fig. 1B laminate of 110+105; [0016]) including a first active region (Fig. 1A RX1; [0016]) and a second active region (Fig. 1A RX2; [0016]),
the first active region (RX1) and the second active region (RX2) extending in a first direction (Fig. 1A extend in Y direction; [0017]),
the first active region (RX1) including a plurality of first active patterns (Fig. 1B FA on RX1; [0017]) spaced apart from each other by a first interval ([0017]),
the second active region (RX2; [0017]) including a plurality of second active patterns (Fig. 1B FA on RX2) spaced apart from each other by a second interval ([0017]);
a device isolation layer (Fig. 1B 112; [0021]) surrounding the first active region (RX1) and the second active region (RX2) on the substrate (laminate of 110+105);
a gate structure (Figs. 1A, 1C GS; [0022]) extending in a second direction (Fig. 1A extend in X direction), the second direction intersecting the first direction (Fig. 1A; [0042]);
a first source/drain region (Fig. 1B 130 on RX1; [0029]) on the first active region (RX1) and a second source/drain region (Fig. 1B 130 on RX2; [0029]) on the second active region (RX2),
the first source/drain region (130 on RX1) and the second source/drain region (130 on RX2) on opposite sides of the gate structure (GS), respectively ([0027]);
an interlayer insulating layer (Figs. 1B, 19D 128; [0028]) on the device isolation layer (112), the interlayer insulating layer (128) covering the gate structure (GS), the first source/drain region (130 on RX1), and the second source/drain region (130 on RX2);
a first contact structure (Fig. 1B CP1 on RX1; [0029]) and a second contact structure (Fig. 1B CP1 on RX2; [0029]) passing through (Fig. 1B) the interlayer insulating layer (128), the first contact structure (CP1 on RX1) and the second contact structure (CP1 on RX2) being connected ([0029]) to the first source/drain region (130 on RX1) and the second source/drain region (130 on RX2), respectively;
a first conductive through-structure (Fig. 1B VC+150; [0029]) electrically connected ([0029]) to the first contact structure (CP1), the first conductive through-structure (VC+150) passing through (Fig. 1B) the substrate (110) and the interlayer insulating layer (128); and
a power delivery structure (Fig. 1B 160; [0033]) extending from a back surface of the substrate (Fig. 1B bottom of laminate of 110+105) toward a front surface of the substrate (Fig. 1B top of laminate of 110+105), the power delivery structure (160) in contact (Fig. 1B; [0033]) with a bottom surface of the first conductive through-structure (bottom of VC+150).
Kim fails to disclose a third active region,
the third active region extending in a first direction,
the second interval being different from the first interval,
the third active region including a plurality of third active patterns spaced apart from each other by a third interval, the third interval being less than the second interval;
an device isolation layer surrounding the third active region on the substrate;
a third source/drain region on the third active region
the first source/drain region, the second source/drain region, and the third drain region on opposite sides of the gate structure, respectively;
the interlayer insulating layer covering the third source/drain region;
a second conductive through-structure electrically connected the second contact structure, the second conductive through-structure passing through the substrate and the interlayer insulating layer; and
a third conductive through-structure extending from a back surface of the substrate toward a front surface of the substrate, the third conductive through-structure connected to the third source/drain region and below the third source/drain region;
the power delivery structures in contact with a bottom surface of the second conductive through-structure and a bottom surface of the third conductive through-structure, respectively, wherein
a level of an upper end of the second conductive through-structure is higher than a level of an upper end of the first conductive through-structure, and
the level of the upper end of the first conductive through-structure is higher than a level of an upper end of the third conductive through-structure.
Chiang discloses a third active region (Fig. 19B 208),
the third active region (Fig. 19B 208; [0049]) extending in a first direction (Fig. 19B X direction,
the third active region (Fig. 19B 208) including a plurality of third active patterns (Fig. 19B 208; [0049]) spaced apart from each other (Fig. 19B);
an device isolation layer (Fig. 18C 230; [0031]) surrounding the third active region (208) on the substrate (208);
a third source/drain region (Fig. 19B 260; [0049]) on the third active region,
the third drain region (260) on opposite sides (Fig. 190B) of the gate structure (Fig. 19B 240’; [0057]),
the interlayer insulating layer (Fig. 19B 270; [0050]) covering the third source/drain region (260);
a third conductive through-structure (Figs. 18D+19B 384; [0072]) extending from the back surface of the substrate (top of 208) toward the front surface of the substrate (bottom of 208), the third conductive through-structure (384) connected (Fig. 19B) to the third source/drain region (260) and below the third source/drain region (Fig. 19B through-structure 384 connects to middle source/drain 260 from backside);
the power delivery structures (Fig. 19B 390; [0075]) in contact (Fig. 19B) with a bottom surface of the third conductive through-structure (384).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Chiang with the device of Kim, Yu, and Wang to create a more power-efficient device to improve device performance.
Chiang fails to explicitly disclose the level of the upper end of the first conductive through-structure is higher than a level of an upper end of the third conductive through-structure. However, one skilled in the art would find it reasonable to add the device of Chiang to the device of Kim to form a third region with the conformation claimed, as disclosed by Kim ([0130]).
The source/drain are at equal levels (Kim Fig. 1B). Chiang discloses the upper surface of the third through-structure 384 to be below the fins 218 with channels 272 (Fig. 19B) while Kim discloses the upper surface of the first through-structure VC+150 to be above the fins FA (Fig. 1B). Therefore, one skilled in the art would make the level of the upper end of the first conductive through-structure higher than a level of an upper end of the third conductive through-structure.
Chiang fails to disclose the second interval being different from the first interval,
the plurality of third active patterns spaced apart from each other by a third interval, the third interval being less than the second interval;
a second conductive through-structure electrically connected the second contact structure, the second conductive through-structure passing through the substrate and the interlayer insulating layer; and
the power delivery structures in contact with a bottom surface of the second conductive through-structure, wherein
a level of an upper end of the second conductive through-structure is higher than a level of an upper end of the first conductive through-structure.
Yu discloses active patterns (Fig. 4 112a-c [0033]; Fig. 35; [0087]-[0090]) spaced apart from each other by different intervals ([0033]; [0087]-[0090]) and intervals being different from each other ([0033]; [0087]-[0090]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to change the second interval to be different from the first interval and to set the interval of the third active patterns to be less than the second interval in the device of Kim as demonstrated by Yu to adjust fin density via routine optimization for the desired device parameters.
Yu fails to disclose a second conductive through-structure electrically connected the second contact structure, the second conductive through-structure passing through the substrate and the interlayer insulating layer; and
the power delivery structures in contact with a bottom surface of the second conductive through-structure, wherein
a level of an upper end of the second conductive through-structure is higher than a level of an upper end of the first conductive through-structure.
Wang discloses a second conductive through-structure (Fig. 21A 720; [0050]-[0054]) electrically connected ([0052]) to the second contact structure (Fig. 21A 730; [0051]; analogous to 130 in RX2 of Kim), the second conductive through-structure (720) passing through the substrate (Fig. 21A 302; [0053]) and the interlayer insulating layer (323); and
the power delivery structure (Fig. 21A 780; [0054]) in contact ([0054]) with a bottom surface of the second conductive through-structure (bottom of 720).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add the frontside interconnection structure and second conductive through-structure of Wang to the device of Kim to provide improved device performance and power efficiency by increasing interconnect density.
Wang fails to explicitly disclose a level of an upper end of the second conductive through-structure is higher than a level of an upper end of the first conductive through-structure However, the upper surface of the second through-structure 720 of Wang is in contact with interlayer insulating layer 750 (analogous to 128 of Kim) and at the same level as the upper surface of source/drain contact 730 (analogous to CP1 of Kim) while the first through-structure VC+150 of Kim contacts the lower surface of the first contact structure (bottom of CP1 in RX1). Therefore, one skilled in the art would make the upper end of the second through-structure would be higher than the upper end of the first through-structure.
Regarding claim 19, Kim, Chiang, Yu, and Wang disclose the semiconductor device of claim 18, further comprising:
a frontside interconnection structure (Wang Fig. 21A 750+760; [0052]) on the front surface of the substrate (Wang top of 302, equivalent to Kim laminate of 110+105), the frontside interconnection structure (750+760) including frontside interconnection patterns (Wang Fig. 21A 760; [0052]); and
a backside interconnection structure (Kim Fig. 1B 170+180) on the back surface of the substrate (Kim bottom of laminate of 110+105), the backside interconnection structure (170+180) including backside interconnection patterns (Kim Fig. 1B 180), wherein
the first conductive through-structure (VC+150) is in contact (Kim Fig. 1B) with a lower portion of the first contact structure (bottom surface of CP1),
the first conductive through-structure (VC+150) is electrically connected (Kim [0029]) to the first source/drain region (130 of RX1) through the first contact structure (CP1), and
the second conductive through-structure (720) is spaced apart (Wang Fig. 21A) from the second contact structure (730),
the second conductive through-structure (720) is in contact (Wang [0052]) with the frontside interconnection structure, and
the second conductive through-structure (720) is electrically connected (Wang [0052]) to the second source/drain region (730) through the frontside interconnection structure (750+760).
Regarding claim 20, Kim, Chiang, Yu, and Wang disclose the semiconductor device of claim 18.
Kim, Chiang, Yu, and Wang fail to explicitly disclose each of the plurality of first active patterns has a first width,
each of the plurality of second active patterns has a second width,
the second width is less than the first width,
each of the plurality of third active patterns has a third width, and
the third width is less than the second width.
However, Yu discloses active patterns having different widths ([0032]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to change the width of the active patterns in the second region to be different from width of the active patterns in the first region via routine optimization to modulate the power consumption and adjust fin density for the desired device parameters.
Conclusion
15. The following art made of record and not relied upon is pertinent to applicant’s disclosure.
Li et al (US 2024/0290657 A1) discloses a semiconductor device with a conductive through-structure in contact with a backside power delivery structure and a source/drain contact
Kim et al (US 2021/0028112 A1) discloses a semiconductor device with a conductive through-structure in contact with a backside power delivery structure and a source/drain contact
Baek et al (US 2022/0059571 A1) discloses a semiconductor device with a conductive through-structure in contact with a backside power delivery structure and a source/drain contact, and in electrical contact with frontside and backside interconnect structures
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/MICHAEL B SUN/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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