DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Applicant’s IDS submitted on 7/8/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
VARIABLE CAPACITANCE OR INDUCTOR ELECTRICALLY CONNECTED TO THE DRAIN OF A TRANSISTOR WHERE THE GATE DIELECTRIC LAYER IS CONTAINED IN THE CAPACITOR OR INDUCTOR
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 13: this claim recites “wherein: an uppermost layer of the dielectric layers is configured as the gate insulating film for the switch, and layers other than the dielectric layer are provided as the gate insulating film to configure the passive element.” Claim 1 requires the gate insulting layer be in the passive element, this claim seems to change that requirement as the upper dielectric layer is gate dielectric, and the bottom dialectic layer is the gate insulating film in the passive device. It is unclear if both layers are gate dielectric layers, and if they are not both gate dielectric layer it is confusing to call the lower layer a gate dielectric layer.
For purposes of examination this claim has been interpreted as the upper layer being a gate dielectric layer and the other layer not being a gate dielectric layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Izumi, US 20040090405 A1 capacitor to drain with separate electrode.
Claims 1-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Goto, JP-2011205017 A hereafter Goto in view of Reig et al., US 20160172113 A1, hereafter Reig.
Regarding claim 1, Goto discloses the following limitations:
An electronic element (Goto, Figure 4, thin film integrated circuit device 11) comprising:
a switch that configures an electric field effect transistor (Goto, Figure 4, TFT 10); and
an element electrically connected to the switch and that configures a passive element (Goto, Figure 4, capacitor 20),
wherein the switch includes:
a source electrode (Goto, Figure 4, source electrode 6s),
a drain electrode (Goto, Figure 4, drain electrode 6d),
a channel forming film (Goto, Figure 4, oxide semiconductor film 3) that overlaps at least a part of the source electrode and a part of the drain electrode (Goto, shown, Figure 4),
a gate insulating film that overlaps the channel forming film (Goto, Figure 4, gate insulating film 4), and
a gate electrode (Goto, Figure 4, gate electrode 7) on the gate insulating film,
wherein the element includes:
a first terminal electrode (Figure 4, wiring 9’) that is electrically connected to the source electrode (Goto, Figure 4, source electrode 6s), and
a second terminal electrode (Goto, Figure 4, first electrode 21) that configures the passive element between the second terminal electrode and a part of the drain electrode (Goto, Figure 4, second electrode 22, which is attached to drain electrode 6d) by sandwiching a dielectric layer therebetween or that is in contact with the dielectric layer (Goto, Figure 4, second electrode 22, and first electrode 21 sandwich gate insulating film 4),
wherein the dielectric layer includes a first dielectric layer that is a same film as at least the gate insulating film (Goto, Figure 4, gate insulating layer 4, and the disclosure “ The gate insulating film 4 is used as a dielectric film 23 of the capacitive element 20”),
Goto fails to disclose the following limitations:
a second dielectric layer
wherein the element configures a plurality of layers of the passive element by sequentially stacking at least a part of the drain electrode, the first dielectric layer, the second terminal electrode, the second dielectric layer, and at least a part of the drain electrode .
Reig discloses the following limitations:
a second dielectric layer (Reig, Figure 9, state change material 8, and 19, disclosed as chalcogenide glass, for example GeTe, GeSe, GeS, AsS or an insulator such as an oxide such as SiO2 or WO3 in [0165])
wherein the element configures a plurality of layers of the passive element by sequentially stacking at least a part of the electrode (Reig, Figure 9, conductive material 3, of first electrode 2), the first dielectric layer (Reig Figure 9, dielectric material 10), the second terminal electrode (Reig, Figure 9, primary electrode 6 and primary electrode 17), the second dielectric layer (Reig, Figure 9, state change material 8 and 19, disclosed as insulator or oxide in [0165]), and at least a part of the electrode (Reig, Figure 9, conductive material 4 of the first electrode 2).
Goto discloses the claimed invention lacking only in not disclosing a variable capacitor attached to the drain electrode. Reig discloses a variable capacitor that has good compatibility with in MOS technology [0017]. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have used the variable capacitor Reig in the device of Goto because Reig teaches that the variable capacitor is compatible with MOS technology and desirably allows the characteristics of a circuit to be modified by changing the capacitive value. It would have further been obvious to have used the same insulting film as the gate oxide film in the capacitive device since Goto uses the film in the capacitor in his circuit and do so would lower cost, as a second insulting layer would not be needed and doing so would also make the device more compact.
Regarding claim 2, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 1, wherein the switch and the element are horizontally disposed on a substrate (Goto, Figure 4, the transistor is to the side horizontally of the capacitor).
Regarding claim 3, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 1, wherein a part of the drain electrode is on a surface of the dielectric layer on a same side as a surface of the gate insulating film on which the gate electrode is disposed (Goto, Figure 4, both drain electrode 6d and gate electrode 7 are bot on top of the gate insulating film 4).
Regarding claim 4, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 3, wherein the second terminal electrode (Goto, Figure 4, 21) is on a surface of the dielectric layer on a side opposite to the surface of the gate insulating film on which the gate electrode is disposed (Goto, Figure 4, electrode 21 and gate electrode 7 on opposite sides of the gate insulating film 4).
Regarding claim 5, the combination of Goto and Reig fail to disclose the following limitations:
The electronic element according to Claim 1, wherein the second terminal electrode is on a surface of the dielectric layer on a same side as a surface of the gate insulating film on which the gate electrode is disposed.
Goto discloses the following:
The electronic element according to Claim 1, wherein the second terminal electrode is on a surface of the dielectric layer on a same side as a surface of the gate insulating film on which the gate electrode is disposed (Goto, discloses “Thin film transistors include structural forms such as an inverted staggered type (bottom gate) and a forward staggered type (top gate).” the device of Goto as pictured in Figure 4 is a top gate design. Goto teaches that top gate and bottom gate transistor are known equivalents in the art. It would have been obvious to one of ordinary skill in the art to substituted one known element (a bottom gate transistor) for another known equivalent (a top gate transistor) resulting in the predictable result of an operable transistor. Such substitution would place the gate electrode under the gate insulting film, and on the same side as electrode 21 in Figure 4 of Goto).
Regarding claim 6, the combination of Goto and Reig fail to disclose the following limitations:
The electronic element according to Claim 5, wherein a part of the drain electrode is on a surface of the dielectric layer on a side opposite to the surface of the gate insulating film on which the gate electrode is disposed (The combination of Goto and Reig as modified for claim 5 above, teach a bottom gate transistor, in such a configuration the drain electrode is on the opposite side of the gate insulting film from the gate electrode).
Regarding claim 7, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 1, wherein a part of the second dielectric layer (Goto, Figure 4, gate-insulating film 4) covers the channel forming film (Goto, Figure 4, oxide semiconductor film 3) between the source electrode and the drain electrode (Goto, Figure 4, gate-insulating film 4, covers the area between 6s and 6d).
Regarding claim 8, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 1, wherein a part of the second terminal electrode (Reig, Figure 9, primary electrode 17) faces a part of the source electrode (Goto, Figure 4, source electrode 6s) with the first dielectric layer sandwiched therebetween (Goto, Figure 4, gate insulating layer, which in the combination would include dialectic material 10, of Reig Figure 9).
Regarding claim 9, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 1, wherein a part of the second terminal electrode (Reig, Figure 9, primary electrode 17) faces a part of the source electrode (Goto, Figure 4, source electrode 6s) with the second dielectric layer (Reig, Figure 9, state change material 8 and 19, disclosed as insulator or oxide in [0165]) sandwiched therebetween .
Regarding claim 10, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 9, wherein a part of the second terminal electrode (Reig, Figure 9, primary electrode 17) faces the channel forming film (Goto, the capacitor is to the right of the transistor so in the combination Reig, 17 faces the channel forming film) with the second dielectric layer sandwiched therebetween (Reig, Figure 9, state change material 8 and 19, disclosed as insulator or oxide in [0165]).
Regarding claim 11, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 1, wherein the passive element is at least one of a capacitor configured by sandwiching the dielectric layer between a part of the drain electrode and the second terminal electrode (Reig, Figure 9, is a capacitor, which when in combination with Goto, Reig 2 would be the drain electrode, and Reig, primary electrode 6 and primary electrode 17 would be the second electrode with the dialectic 10 in between), an inductor configured with a coil electrode that connects a part of the drain electrode to the second terminal electrode, and a resistor configured with a resistor element that connects a part of the drain electrode to the second terminal electrode.
Regarding claim 13, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 2, wherein:
an uppermost layer of the dielectric layers is configured as the gate insulating film for the switch (Goto, Figure 4 insulating layer 4), and
layers other than the dielectric layer are provided as the gate insulating film to configure the passive element (Reig in combination with Goto, disclose the use of layers other than the gate insulating layer in the capacitor, Reig, Figure 4, state change material 8, disclosed as insulator or oxide in [0165], which is lower than layer 10, the gate insulating film in the combination).
Regarding claim 14, the combination of Goto and Reig disclose the following limitations:
A circuit device comprising:
a circuit wiring line (Goto, Figure 4, Power supply wiring 9); and
the electronic element according to Claim 1 that is electrically connected to the circuit wiring line (The combination of Goto and Reig teach the limitans of claim 1, as detailed above).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Goto and Reig as applied to claim 1 above and further in view of Chi et al., US 6362012 B1, hereafter Chi.
Regarding claim 12, Goto and Reig discloses the limitans of claim 1, as detailed above. Goto and Reig fail to disclose the following limitations:
The electronic element according to Claim 1, wherein the passive element is an inductor, and the first and second terminal electrodes are connected to each other with a wiring line.
Chi discloses the following limitations:
the passive element is an inductor, and the first and second terminal electrodes are connected to each other with a wiring line (Chi, Figure 1b , multi-layered spiral inductor 20 connects input and output points 26 and 28, which are the two terminals of the inductor 20)
Goto discloses a capacitor connected to the drain electrode of a transistor, where the capacitor where the gate insulating film is used in the structure of the capacitor. Chi discloses a multi-layer inductor fabricated from metal and insulative layer, and connected to the drain electrode of a transistor that contains stacks of metal layers and insulting layers. The difference between the prior art and the claimed invention is connecting an inductor instead of a capacitor to the drain of a transistor. Since all of the claimed elements would continue to operate in the same manner, specifically the inductor would operate as and inductor in the circuit of Goto. Therefore the results would be predictable to one of ordinary skill in the art. As such, it would have been obvious to one of ordinary skill in the art to have used an inductor in place of the capacitor in the device of Goto as such would be not more “than the predictable use of prior art elements according to their established functions.” In such a combination it would have further ben obvious to ne used the gate insulting layer in the inductor since Goto teaches to use the gate insulating layer in a passive device and doing so would reduce processing steps and make a more compact device.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Goto in view of Reig and Chi et al., US 6362012 B1, hereafter Chi.
Regarding claim 15, the combination of Goto disclose the following limitations (The lined out items are limitations that Goto does not disclose):
An electronic element (Goto, Figure 4, thin film integrated circuit device 11) comprising:
a switch that configures an electric field effect transistor (Goto, Figure 4, TFT 10); and
an element electrically connected to the switch and that configures
wherein the switch includes:
a source electrode (Goto, Figure 4, source electrode 6s),
a drain electrode (Goto, Figure 4, drain electrode 6d),
a channel forming film (Goto, Figure 4, oxide semiconductor film 3) that overlaps at least a part of the source electrode and a part of the drain electrode (Goto, shown, Figure 4),
a gate insulating film that overlaps the channel forming film (Goto, Figure 4, gate insulating film 4), and
a gate electrode (Goto, Figure 4, gate electrode 7) on the gate insulating film,
wherein the element includes:
a first terminal electrode (Figure 4, wiring 9’) that is electrically connected to the source electrode (Goto, Figure 4, source electrode 6s), and
a second terminal electrode (Goto, Figure 4, first electrode 21) that configures (Goto, Figure 4, second electrode 22, which is attached to drain electrode 6d) by sandwiching a dielectric layer therebetween or that is in contact with the dielectric layer (Goto, Figure 4, second electrode 22, and first electrode 21 sandwich gate insulating film 4), and
wherein the dielectric layer and the gate insulating film are a same insulating film (Goto, Figure 4, gate insulating layer 4, and the disclosure “ The gate insulating film 4 is used as a dielectric film 23 of the capacitive element 20”), and
Goto fails to disclose the following limitations:
An inductor
wherein the first terminal electrode, the drain electrode, and the second terminal electrode are on a surface of the dielectric layer on a side opposite to a surface of the gate insulating film on which the gate electrode is disposed.
Chi discloses the following limitations:
An inductor (Chi, Figure 1b , multi-layered spiral inductor 20 connects input and output points 26 and 28, which are the two terminals of the inductor 20)
Goto discloses a capacitor connected to the drain electrode of a transistor, where the capacitor where the gate insulating film is used in the structure of the capacitor. Chi discloses a multi-layer inductor fabricated from metal and insulative layer, and connected to the drain electrode of a transistor that contains stacks of metal layers and insulting layers. The difference between the prior art and the claimed invention is connecting an inductor instead of a capacitor to the drain of a transistor. Since all of the claimed elements would continue to operate in the same manner, specifically the inductor would operate as and inductor in the circuit of Goto. Therefore the results would be predictable to one of ordinary skill in the art. As such, it would have been obvious to one of ordinary skill in the art to have used an inductor in place of the capacitor in the device of Goto as such would be not more “than the predictable use of prior art elements according to their established functions.” In such a combination it would have further ben obvious to ne used the gate insulting layer in the inductor since Goto teaches to use the gate insulating layer in a passive device and doing so would reduce processing steps and make a more compact device.
Goto and Chi fail to disclose the following limitations:
wherein the first terminal electrode, the drain electrode, and the second terminal electrode are on a surface of the dielectric layer on a side opposite to a surface of the gate insulating film on which the gate electrode is disposed (Goto, discloses “Thin film transistors include structural forms such as an inverted staggered type (bottom gate) and a forward staggered type (top gate).” the device of Goto as pictured in Figure 4 is a top gate design. Goto teaches that top gate and bottom gate transistor are known equivalents in the art. It would have been obvious to one of ordinary skill in the art to substituted one known element (a bottom gate transistor) for another known equivalent (a top gate transistor) resulting in the predictable result of an operable transistor. Such substitution would place the gate electrode under the gate insulting film, and on the same side as electrode 21 in Figure 4 of Goto).
Regarding claim 16, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 15, wherein the switch and the element are horizontally disposed on a substrate (Goto, Figure 4, the transistor is to the side horizontally of the capacitor in combination which Chi replacing the capacitor with an inductor).
Regarding claim 17, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 15, wherein the dielectric layer includes a first dielectric layer that is a same film as at least the gate insulating film, and a second dielectric layer (Chi, Figure 1b , multi-layered spiral inductor 20 connects input and output points 26 and 28, which are the two terminals of the inductor 20. In combination with Goto who discloses using the insulating layer in a passive device, and doing so would make a more compact device and reduce processing steps.).
Regarding claim 18, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 17, wherein a part of the second dielectric layer covers the channel forming film between the source electrode and the drain electrode (Chai, Figure 2b, upper insulation layers cover the transistor).
Regarding claim 19, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 17, wherein a part of the second terminal electrode (Goto, Figure 4, first electrode 21, replaced in the combination by input and output terminal 28 of Chi) faces a part of the source electrode (Goto, Figure 4, source electrode 6s) with the first dielectric layer sandwiched therebetween (Chi, Figure 1b input/output terminal 28 runs up the inductor, therefore a portion of 28 will sandwich the first dielectric layer with the source electrode).
Regarding claim 20, the combination of Goto and Reig disclose the following limitations:
The electronic element according to Claim 17, wherein:
a part of the second terminal electrode (Goto, Figure 4, first electrode 21, replaced in the combination by input and output terminal 28 of Chi) faces a part of the source electrode (Goto, Figure 4, source electrode 6s) with the first dielectric layer sandwiched therebetween (Chi, Figure 1b input/output terminal 28 runs up the inductor, therefore a portion of 28 will sandwich the first dielectric layer with the source electrode), and
a part of the second terminal electrode (Goto, Figure 4, first electrode 21, replaced in the combination by input and output terminal 28 of Chi) faces the channel forming film (Goto, Figure 4, semiconductor film 3) with the second dielectric layer sandwiched therebetween (Chi, Figure 1b input/output terminal 28 runs up the inductor, therefore a portion of 28 will sandwich the first dielectric layer with the channel forming film).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park, US 20190206328 A1, discloses a transistor with a variable capacitor connected to the source and drain.
Ray et aal., US 20080039025 A1, discloses the use of a variable capacitor and inductor connected to the drain as a harmonic termination circuit that allows for two modes of operation.
Baeck et al., US 20250220956 A1, discloses the use of the gate insulting layer in a capacitor attached to the source of a transistor.
Jang, et al., US 20250241008 A1, discloses the use of the gate insulting layer in a stacked capacitor attached to the source of a transistor, where the source is connected to the top and bottom electrode and the gate is connected to the middle electrode.
Zakharian, US 6608405 B1, discloses variable capacitors and their use in place of non-adjustable capacitors.
Miyasko et al., US 20230246040 A1, discloses a variable capacitor with multiple electrodes including a drain electrode on the top and bottom and a different electrode in between, attached to the drain.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET.
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/LINDA J. FLECK/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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