DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/12/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an amplification controller coupled to the at least one differential amplification stage” in Claim 10 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2-10 & 14-21 are objected to because of the following informalities:
In Claims 2-10, line 1, each discloses the limitations “Differential” should change to read ---The differential--.
In Claims 14-21, line 1, each discloses the limitations “Method” should change to read ---The method--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 4, lines 4 & 6, the recitation of “controllably transmit at least a part of the signal” is not clear because the “the signal” is not clearly defined and lack of antecedent basis and how a part of the signal would be separated before transmit a part of the signal. Further clarification is needed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 8-13, 15-18 & 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over
ITABASHI et al. (US 20170117860 A1, hereinafter, Itabashi) in view of Sedighi (US 20240063765 A1).
Regarding claims 1 & 13:
Itabashi discloses in Fig. 1, differential signal amplification system or method comprising:
a differential input transmission line arrangement comprising a positive input signal transmission line (Fig. 1: line 31a), and a negative input signal transmission line (line 31b);
a differential output transmission line arrangement comprising a positive output signal transmission line (line 32a), and a negative output signal transmission line (line 32b);
at least one differential amplification stage (Cell_1, Cell_N) coupled to the differential input transmission line arrangement, and the differential output transmission line arrangement
Itabashi fails to disclose:
wherein the at least one differential amplification stage comprises a signal transmission matrix configured to at least one of: controllably transmit a positive input signal from a positive signal input of the signal transmission matrix at least in part to at least one of a negative signal output of the signal transmission matrix and a positive signal output of the signal transmission matrix; and controllably transmit a negative input signal from a negative signal input of the signal transmission matrix at least in part to at least one of the positive signal output, and the negative signal output.
Sedighi disclose in Fig. 3A a differential amplifier circuit comprising:
wherein the at least one differential amplification stage (300A of Fig. 3A) comprises a signal transmission matrix (Fig. 3A of Sedighi discloses a circuit that includes transistors 302, 304, 306, 308, 310, 312 which having similarly arrangement to the Fig. 6 of the application) configured to at least one of: controllably transmit a positive input signal (see details Fig. 3A) from a positive signal input of the signal transmission matrix at least in part to at least one of a negative signal output (see details Fig. 3A) of the signal transmission matrix and a positive signal output of the signal transmission matrix; and controllably transmit a negative input signal from a negative signal input of the signal transmission matrix at least in part to at least one of the positive signal output, and the negative signal output.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced generic differential amplifier of Itabashi with specific differential amplifier as taught by Sedighi in order to provide the benefits of improving power efficiency (see paragraph [0026]), lower power consumption (see, [0039]) and reducing sensitivity (abstract).
Regarding claims 3 & 15:
The combination (Itabashi in view of Sedighi) further discloses the differential signal amplification system according to claim 1, wherein the differential amplification stage further comprises at least one of: a positive amplifier (transistor 204a) arranged between the positive input signal transmission line (31a), and the positive signal input of the signal transmission matrix (node between transistors302, 306 and transistor 204a); and a negative amplifier (transistor 204b) arranged between the negative input signal transmission line (31b), and the negative signal input of the signal transmission matrix (node between transistors 304, 308 and transistor 204b).
Regarding claims 4 & 16:
The combination (Itabashi in view of Sedighi) further discloses the differential signal amplification system according to claim 1, wherein the signal transmission matrix comprises a plurality of transmission elements (transistors 302, 304, 306, 308, 310, 312) that are configured to at least one of: controllably transmit at least a part of the signal received via the positive signal input to the negative signal output and the positive signal output (noted that the similarly arrangement as discussed above in Fig. 3A, control signals amp1, amp2, amp3 as shown in Fig. 3A); and controllably transmit at least part of the signal received via the negative signal input to the positive signal output and the negative signal output (note that the similarly arrangement as discussed above in Fig. 3A).
Regarding claims 5 & 17:
The combination (Itabashi in view of Sedighi) further discloses the differential signal amplification system according to claim 1, wherein the signal transmission matrix comprises a first positive transmission element (Fig. 3A: transistor 310), and a second positive transmission element (302), a first negative transmission element (312), and a second negative transmission element (304); wherein the first positive transmission element is coupled between the positive signal input (Vip), and the negative signal output (Vom); wherein the second positive transmission element (302) is coupled between the positive signal input (Vip), and the positive signal output (Vop); wherein the first negative transmission element is coupled between the negative signal input (Vim), and the positive signal output (Vop); and wherein the second negative transmission element is coupled between the negative signal input (Vim), and the negative signal output (Vom).
Regarding claims 6 & 18:
The combination (Itabashi in view of Sedighi) further discloses the differential signal amplification system according to claim 5, wherein the first positive transmission element (310), the second positive transmission element (302), the first negative transmission element (312), and the second negative transmission element (304) are configured to controllably transmit a variable part of an input signal from the respective signal input to the respective signal output.
Regarding claims 8 & 20:
The combination (Itabashi in view of Sedighi) further discloses the differential signal amplification system according to claim 5, wherein the first positive transmission element, the second positive transmission element, the first negative transmission element, and the second negative transmission element each comprise a switch (transistor which function as switch, see transistors 310, 302, 312, 304).
Regarding claims 9 & 21:
The combination (Itabashi in view of Sedighi) further discloses the differential signal amplification system according to claim 8, wherein the signal transmission matrix further comprises a third positive transmission element (306), and a third negative transmission element (308); wherein the third positive transmission element is coupled between the positive signal input, and the negative signal output; wherein the third negative transmission element is coupled between the negative signal input, and the positive signal output; and wherein the third positive transmission element, and the third negative transmission element each comprise a switch (see transistors 306, 308).
Regarding claim 10:
The combination (Itabashi in view of Sedighi) discloses the differential signal amplification system according to claim 1, further comprising an amplification controller (para. 43, e.g., control voltage labelled amp1 which intended for controller to control these node amp1, amp2, amp3 as shown in Fig. 3A) coupled to the at least one differential amplification stage, and configured to at least one of: control the signal transmission matrix (Fig. 3A, transistors 302, 304, 306, 308, 310, 312) to output signals received on the positive signal input via the negative signal output, and signals received on the negative signal input via the positive signal output; control the signal transmission matrix to output signals received on the positive signal input via the positive signal output, and signals received on the negative signal input via the negative signal output; and control the signal transmission matrix (Fig. 3A, transistors 302, 304, 306, 308, 310, 312) to destructively combine signals received on the positive signal input, and the negative signal input on the positive signal output, and the negative signal output.
Regarding claim 11:
Itabashi discloses in Fig. 1, measurement application device comprising:
a differential signal input comprising a positive signal input port (Dina), and a negative signal input port (Dinb);
a measurement signal processing arrangement (Line 32a, line 32b) comprising a positive input port (a port between Cell_1 and Louta_0), and a negative input port (a port between Cell_1 and Loutb_0);
a first differential signal amplification system comprising:
a differential input transmission line arrangement comprising a positive input signal transmission line (line 31a) coupled to the positive signal input port (Dina), and a negative input signal transmission line (31b) coupled to the negative signal input port (Dinb);
a differential output transmission line arrangement (lines 32a, 32b) comprising a positive output signal transmission line (32a) coupled to the positive input port, and a negative output signal transmission line (32b) coupled to the negative input port;
at least one differential amplification stage (Cell_1) coupled to the differential input transmission line arrangement, and the differential output transmission line arrangement.
Itabashi fails to disclose:
wherein the at least one differential amplification stage comprises a signal transmission matrix configured to at least one of: controllably transmit a positive input signal from a positive signal input of the signal transmission matrix at least in part to at least one of a negative signal output of the signal transmission matrix and a positive signal output of the signal transmission matrix; and controllably transmit a negative input signal from a negative signal input of the signal transmission matrix at least in part to at least one of the positive signal output, and the negative signal output.
Sedighi disclose in Fig. 3A a differential amplifier circuit comprising the at least one differential amplification stage comprises a signal transmission matrix (Fig. 3A of Sedighi discloses a circuit that includes transistors 302, 304, 306, 308, 310, 312 which having similarly arrangement to the Fig. 6 of the application) configured to at least one of: controllably transmit a positive input signal (analogous arrangement, see details Fig. 3) from a positive signal input of the signal transmission matrix at least in part to at least one of a negative signal output (analogous, see details Fig. 3A) of the signal transmission matrix and a positive signal output of the signal transmission matrix; and controllably transmit a negative input signal from a negative signal input of the signal transmission matrix at least in part to at least one of the positive signal output, and the negative signal output.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced generic differential amplifier of Itabashi with specific differential amplifier as taught by Sedighi in order to provide the benefits of improving power efficiency (see paragraph [0026]), lower power consumption (see, [0039]) and reducing sensitivity (abstract).
Regarding claim 12:
Itabashi discloses in Fig. 1, measurement application device comprising a differential signal amplification system comprising: a differential input transmission line arrangement comprising
a positive input signal transmission line (31a) coupled to a positive signal input port (Dina), and
a negative input signal transmission line (31b) coupled to a negative signal input port (Dinb);
a differential output transmission line arrangement comprising a positive output signal transmission line (32a) coupled to the positive signal input port, and
a negative output signal transmission line (32b) coupled to the negative signal input port; at least one differential amplification stage (Cell_1) coupled to the differential input transmission line arrangement, and the differential output transmission line arrangement.
Itabashi fails to disclose:
wherein the at least one differential amplification stage comprises a signal transmission matrix configured to at least one of: controllably transmit a positive input signal from a positive signal input of the signal transmission matrix at least in part to at least one of a negative signal output of the signal transmission matrix and a positive signal output of the signal transmission matrix; and controllably transmit a negative input signal from a negative signal input of the signal transmission matrix at least in part to at least one of the positive signal output, and the negative signal output; wherein the differential output transmission line arrangement of the first differential signal amplification system is coupled to the differential input transmission line arrangement of the second differential signal amplification system.
Sedighi disclose in Fig. 3A a differential amplifier circuit comprising wherein the at least one differential amplification stage comprises a signal transmission matrix (includes transistors 302, 304, 306, 308, 310, 312 which having similarly arrangement to the Fig. 6 of the application) configured to at least one of: controllably transmit a positive input signal from a positive signal input of the signal transmission matrix at least in part to at least one of a negative signal output of the signal transmission matrix and a positive signal output of the signal transmission matrix; and controllably transmit a negative input signal from a negative signal input of the signal transmission matrix at least in part to at least one of the positive signal output, and the negative signal output; wherein the differential output transmission line arrangement of the first differential signal amplification system is coupled to the differential input transmission line arrangement of the second differential signal amplification system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced generic differential amplifier of Itabashi with specific differential amplifier as taught by Sedighi in order to provide the benefits of improving power efficiency (see paragraph [0026]), lower power consumption (see, [0039]) and reducing sensitivity (abstract).
Allowable Subject Matter
Claims 2, 7, 14 & 19, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2 & 14 are allowable since the combination (Itabashi in view of Sedighi) does not disclose wherein the differential amplification stage further comprises at least one of: a positive bias control circuitry arranged between the positive output signal transmission line, and the positive signal output of the signal transmission matrix; and a negative bias control circuitry arranged between the negative output signal transmission line, and the negative signal output of the signal transmission matrix.
Claims 7 & 19 are allowable since the combination (Itabashi in view of Sedighi) does not disclose wherein the first positive transmission element, the second positive transmission element, the first negative transmission element, and the second negative transmission element each comprise an amplifier; and wherein each one of the amplifiers comprises a controllable gain.
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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