Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I, described by claims 1-12 and drawn to a semiconductor chip and a semiconductor package, in the reply filed on 07/13/2026 is acknowledged.
The traversal is on the ground(s) that the applicant contends that the search and examination of all the claims may be made without a serious burden. This argument is not found persuasive because inventions I and II are classified in different areas: invention I (claims 1-12), drawn to a semiconductor chip and a semiconductor package is classified in H10W 72/942 and invention 2 (claims 13-20) drawn to a method of manufacturing a semiconductor chip, is classified in classified in H10W 20/021. The inventions are independent or distinct, each from the other because the inventions have acquired a separate status in the art in view of their different classifications. Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claims 8 and 11 are objected to because of the following informalities:
Regarding claim 8, the claim says, “wherein the insulation structure is at an entire region other than the capping pad on the insulation layer.” This is not grammatically correct or logically sensible, as the “entire region” is required to be “other than the capping pad.” This claim might be corrected by defining this region in comparison to another region rather than in comparison to a capping pad. Appropriate correction is required.
Regarding claim 9, states “the insulation structure is partially in an edge region that is along an edge of the semiconductor chip at an outside of the capping pad.” This wording is awkward enough to cause confusion. Possible corrections include “at a position outside of” or at an outside edge of. “ Appropriate correction is required.
Regarding claim 11, this claim teaches “the semiconductor chip of claim 1, wherein the semiconductor chip is used for a fan-out panel level package.” MPEP 2114. II says that the manner of operating the device does not differentiate an apparatus claim from the prior art. That is, apparatus claims should cover what a device is, not what a device does. A possible correction would be to claim a device “configured to …” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 20220068730.
Regarding claim 1, Kim discloses a semiconductor chip, comprising:
a semiconductor substrate (figure 7, element 110 is the semiconductor substrate [0031]);
an interconnection pad on a first surface of the semiconductor substrate (figure 7 shows that the interconnection pad 120 is located on a first surface of the substrate 110 [0034]);
an insulation layer on the first surface of the semiconductor substrate (barrier layer 130 is on the first (lower in figure 7) surface of the semiconductor substrate 110 [0048]),
the insulation layer defining an opening that exposes at least a partial portion of the interconnection pad (figure 6 shows that layer 130 defines an opening in the substrate 110 that exposes the interconnection pad 120 [0049]);
a capping pad on the insulation layer (figure 7, layer 600 is a capping pad on the insulation layer 130 [0115]),
the capping pad being connected to the interconnection pad through the opening (capping pad 600 and interconnection pad 120 through the connection portion 120_CA through the opening [0038]); and
an insulation structure at a periphery of the capping pad on the insulation layer (figure 7 shows molding layer 310, which is located at the periphery of the capping pad 600 on the insulation layer 130, [0075]).
Regarding claim 2, Kim discloses the semiconductor chip of claim 1, wherein an outer surface of the insulation structure and an outer surface of the capping pad are on a same plane (as shown in the annotated figure 7 below, the outer (here defined as the right surfaces in figure 7) of the isolation structure 130 and the capping pad 600 are on the same plane).
Regarding claim 3, Kim discloses the semiconductor chip of claim 1, wherein each of an outer surface of the insulation structure and an outer surface of the capping pad includes a flat surface (annotated figure 7 below shows that an outer surface, where the outer surface is defined as the right surface, of the insulation structure 130 and an outer surface of the capping pad 600 each includes a flat surface).
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Regarding claim 4, Kim discloses the semiconductor chip of claim 1, wherein an outer surface of the capping pad has a height variation of l μm or less (Annotated figure 7 above shows that an outer surface of the capping pad is planar, therefore the height variation, 0 μm, is less than l μm), and a height difference between the outer surface of the insulation structure and an outer surface of the capping pad is l μm or less (Annotated figure 7 above shows that an outer surface of the capping pad is coplanar with an outer surface of the capping layer, therefore the height variation, 0 μm, is less than l μm.)
Regarding claim 5, Kim discloses the semiconductor chip of claim 1, wherein a height variation at an outer surface of the capping pad is smaller than a height variation at an inner surface of the capping pad adjacent to the insulation layer and the interconnection pad, or a height variation at the outer surface of the capping pad is smaller than a thickness of the insulation layer or a thickness of the interconnection pad (As shown in the rejection of claim 4 above, an outer surface of the capping pad is planar, therefore the height variation is zero, while annotated figure 7 below shows that than a height variation at an inner surface of the capping pad
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600 adjacent to the insulation layer 130 and the interconnection pad 120 is greater than zero.
[AltContent: connector]Regarding claim 6, Kim discloses the semiconductor chip of claim 1, wherein the capping pad includes a first portion that fills the opening and is connected to the interconnection pad and a second portion on the insulation layer (See annotated figure 7 below, where two portions of layer 600 are marked) and a thickness of the second portion is larger than a thickness of the insulation layer, a thickness of the interconnection pad, or a sum of the thickness of the insulation layer and the thickness of the interconnection pad.( Since the thickness in the horizontal direction of the second portion of the capping layer 600 is the same as the width of the opening, annotated figure 7 clearly shows that the thickness of the second portion is larger than the thickness of the interconnection pad 120.)
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Regarding claim 7, Kim discloses the semiconductor chip of claim 1, wherein the capping pad includes a first portion that fills the opening and is connected to the interconnection pad and a second portion on the insulation layer, and a thickness of the second portion is 5 μm to 15 μm (Paragraph [0117] discloses that layer 600, the capping pad, may have a thickness in the vertical direction of figure 7 of 1 μm to 5 μm, and paragraph [0055} discloses that the opening in the barrier layer 130, which is the same thickness in the horizontal direction as capping layer 600, is 10 μm -50 μm. Since the entirety of the capping pad 600 is on the insulation layer 130, it is possible choose a second portion that has a thickness of 5 μm to 15 μm, as illustrated schematically below:
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Regarding claim 8, Kim discloses the semiconductor chip of claim 1, wherein the insulation structure is at an entire region other than the capping pad on the insulation layer (The embodiment of the semiconductor 40 in figure 8 is the same as the embodiment 30 in figures 6 and 7, excepting the addition of the embedded frame 490 in figure 8 as described in paragraph [0133]. Annotated figure 8 shows that insulation structure 490 is in a region separate from the region of the capping pad 600 on the on the insulation layer 130.)
Regarding claim 9, Kim discloses the semiconductor chip of claim 1, wherein the insulation structure is partially in an edge region that is along an edge of the semiconductor chip at an outside of the capping pad (Annotated figure 8 below shows that the insulation structure 490 is outside of the capping pad 600 and at an edge region of the semiconductor chip 100.)
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Regarding claim 10, Kim discloses the semiconductor chip of claim 1, wherein the insulation structure includes a photosensitive material or an epoxy mold compound (EMC) (paragraph [0075] discloses that the layer 310 may include an epoxy molding compound (EMC)).
Regarding claim 11, Kim discloses the semiconductor chip of claim 1, wherein the semiconductor chip is used for a fan-out panel level package (FoPLP) (paragraph [0135] discloses that the semiconductor chip of claim 1 may be configured to be used in a FoPLP – the embodiment of the semiconductor 40 is the same as the embodiment 30 excepting the addition of the embedded frame 490 in figure 8 as described in paragraph [0133]).
Regarding claim 12, Kim discloses a semiconductor package, comprising:
a redistribution portion (layer 200 in figure 6, which illustrates the same embodiment as figure 7 [0114]); and
a semiconductor chip on the redistribution portion (semiconductor chip 100 is on the redistribution portion 200, see paragraph [0114] and figure 6), wherein the semiconductor chip includes:
a semiconductor substrate (figure 7, element 110 is the semiconductor substrate [0031]);
an interconnection pad on a first surface of the semiconductor substrate (figure 7 shows that the interconnection pad 120 is located on a first surface of the substrate 110 [0034]);
an insulation layer on the first surface of the semiconductor substrate (barrier layer 130 is on the first (lower in figure 7) surface of the semiconductor substrate 110 [0048]),
the insulation layer defining an opening that exposes at least a partial portion of the interconnection pad (figure 6 shows that layer 130 defines an opening in the substrate 110 that exposes the interconnection pad 120 [0049]);
a capping pad on the insulation layer (figure 7, layer 600 is a capping pad on the insulation layer 130 [0115]),
the capping pad being connected to the interconnection pad through the opening and to the redistribution portion (capping pad 600 and interconnection pad 120 through the connection portion 120_CA through the opening [0038]); and
an insulation structure at a periphery of the capping pad on the insulation layer (figure 7 shows molding layer 310, which is located at the periphery of the capping pad 120 on the insulation layer 130, [0075]),
the insulation structure being adjacent to the redistribution portion (the insulation structure, molding layer 310 is adjacent to the redisposition portion, as illustrated in figure 6).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
J. H. Lau, "Recent Advances and Trends in Advanced Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 2, pp. 228-252, Feb. 2022. (Defines and explains methods of advance packaging, including fan-out level packaging.)
Park et al. US 20200194362 (Describes a similar semiconductor package from Samsung)
Meyer et al. US 20120208319 (Discloses a packaged semiconductor device including a chip embedded in encapsulant and with contact pads)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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