Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 11 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Choi et al. (US-20220262721-A1 referred as Choi).
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Regarding claim 1. Choi discloses a semiconductor device, comprising:
a substrate including a cell array region, a core region, and a peripheral circuit region ([0016], figure 2B annotated above, a substrate #301 includes a cell array region #CA, a core region #PA, and a peripheral circuit region #P-Region);
a core circuit wiring on the core region of the substrate ([0032], figure 2B, core circuit wiring #UM2 on the core region #PA of the substrate #301);
a core signal wiring overlapping the core circuit wiring ([0032], figure 2B, a core signal wiring #343bw overlapping the core circuit wiring #UM2); and
a contact plug between the core circuit wiring and the core signal wiring and connecting the core circuit wiring to the core signal wiring ([0032], figure 2B, contact plug #MC between the core circuit wiring #UM2 and the core signal wiring #343bw and connecting both elements), wherein
a positional relationship between the core signal wiring and the contact plug is different depending on a distance of the contact plug from the peripheral circuit region ([0016], figure 2B annotated above, a positional relationship between the core signal wiring #343bw and the contact plug #MC is different depending on a distance from the contact plug #MC from the peripheral circuit region #P-Region).
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Regarding claim 2. Choi discloses wherein the core signal wiring comprises a first edge and a second edge opposite the first edge ([0016], figure 2B annotated close up above, the core signal wiring #343bw-right has a first edge #1E and a second edge #2E opposite of first edge #1E),; the first edge is closer to the peripheral circuit region than the second edge ([0016], figure 2B annotated close up above, the first edge #1E is closer to the peripheral circuit region #P-Region than the second edge #2E); a first distance from the first edge of the core signal wiring to the contact plug gradually increases as the distance of contact plug from the peripheral circuit region increases ([0016], figure 2B annotated close up above, a first distance #1D from the first edge #1E of the core signal wiring #343bw-right to the contact plug #MC gradually increases as the distance from the contact plug #MC from the peripheral circuit region #P-Region increases (as seen when the right core signal wiring #343-right is compared to the left core signal wiring #343-left)).
Regarding claim 3. Choi discloses wherein a second distance from the second edge of the core signal wiring to the contact plug gradually decreases as the distance of the contact plug from the peripheral circuit region increases ([0016], figure 2B annotated close up above, a second distance #2D from the second edge #2E of the core signal wiring #343-right gradually decreases as the of the contact plug #MC from the peripheral circuit region #P-Region increase (as seen when the right core signal wiring #343-right is compared to the left core signal wiring #343-left)).
Regarding claim 11. Choi discloses wherein a positional relationship between the core circuit wiring and the contact plug is constant regardless of the distance of the contact plug from the peripheral circuit region ([0016], figure 2B annotated above, a positional relationship between the core signal wiring #343bw and the contact plug #MC is constant regardless of the distance from the contact plug #MC to the peripheral circuit region #P-Region).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US-20220262721-A1 referred as Choi) in view of Kim et al. (US-20240074165-A1 referred as Kim).
Regarding claim 12. Choi discloses a word line on the cell array region of the substrate ([0016], figure 1, a word line #WL on the cell array region #CA);
a bit line crossing the word line ([0016], figure 1-2B, a bit line #BL crossing the word line #WL);
a bit line contact pattern connecting between a first active region of the substrate and the bit line ([0019], figure 1, the first active region #ACTC includes a region #305a within. As described in [0024], a bit line contact pattern #DC connects the first active region #ACTC/305a to the bit line #BL).
Choi lacks a landing pad connected to the first active region of the substrate; and
a lower contact between the landing pad and the first active region of the substrate an connecting the landing pad to the first active region, wherein
the core circuit wiring is in a same layer as the landing pad.
Kim discloses a landing pad connected to the first active region of the substrate ([0042], figure 3b, a landing pad #221 (far left element) is connected to the first active region #203 of the substrate #201); and
a lower contact between the landing pad and the first active region of the substrate an connecting the landing pad to the first active region ([0042], figure 3b, a lower contact #210 is connected in between the landing pad #221 and the first active region #203), wherein
the core circuit wiring is in a same layer as the landing pad ([0042], figure 3b, the core circuit wiring #221 (the elements on the right side) is in a same layer as the landing pad #221 (far left element).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Choi to include a landing pad, lower contact, and core circuit wiring as taught by Kim in order to have improved electrical performance, better signal integrity, and for enhanced heat management.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US-20220262721-A1 referred as Choi) in view of Lee et al. (US-20200365706-A1 referred as Lee).
Regarding claim 14. Choi lacks a gate stack on the core region of the substrate, wherein the substrate includes an impurity region positioned at both sides of the gate stack, and the core circuit wiring is connected to the impurity region.
Lee discloses a gate stack on the core region of the substrate, wherein the substrate includes an impurity region positioned at both sides of the gate stack, and the core circuit wiring is connected to the impurity region ([0053], figure 1B, a gate stack #GS on the core region #A-A of the substrate #101, wherein the substrate #101 includes impurity regions #123 positioned at both sides of the gate stack #GS. And the core circuit wiring #193 is connected to the impurity region #123 as described in [0160]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Choi to include gate stacks and impurity regions as taught by Lee in order to have enhanced channel control, improved device performance, and to increase device versatility.
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US-20220262721-A1 referred as Choi) in view of Hong (US-20150108663-A1).
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Regarding claim 15. Choi discloses a semiconductor device, comprising: a substrate including a peripheral circuit region ([0016], figure 2B annotated above, a substrate #301 includes a peripheral circuit region #P-Region);
a core circuit wiring on the core region of the substrate ([0032], figure 2B, core circuit wiring #UM2 on the core region #PA of the substrate #301);
a core signal wiring overlapping the core circuit wiring ([0032], figure 2B, a core signal wiring #343bw overlapping the core circuit wiring #UM2); and
a contact plug between the core circuit wiring and the core signal wiring and connecting the core circuit wiring to the core signal wiring ([0032], figure 2B, contact plug #MC between the core circuit wiring #UM2 and the core signal wiring #343bw and connecting both elements), wherein
a first distance from a first edge of the core signal wiring to the contact plug gradually changes as a distance of the contact plug from the peripheral circuit region increases ([0016], figure 2B annotated close up above, a first distance #1D from the first edge #1E of the core signal wiring #343bw-right to the contact plug #MC gradually changed as the contact plug #MC to the peripheral circuit region #P-Region increases (as seen when the right core signal wiring #343-right is compared to the left core signal wiring #343-left)).
Choi lacks a plurality of cell array regions at both sides of the peripheral circuit region and arranged along a first direction and a second direction, and a core region between the plurality of cell array regions.
Hong discloses a plurality of cell array regions at both sides of the peripheral circuit region and arranged along a first direction and a second direction, and a core region between the plurality of cell array regions ([0052], figure 3, a plurality of cell array regions #CA at both sides of the peripheral circuit region #PERI. [0054], figure 4, and a core region #BLK between the plurality of cell array regions #PERI).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Choi to include a plurality of cell array regions at both sides of the peripheral circuit region and a core region as taught by Hong in order to enhance the device integrity, distribute weight across the device, and to extend the devices lifetime.
Regarding claim 16. Choi as modified discloses wherein the core signal wiring comprises a second edge opposite the first edge ([0016], figure 2B annotated close up above, the core signal wiring #343-right comprises a second edge #2E opposite of the first edge #1E); the first edge is closer to the peripheral circuit region than the second edge ([0016], figure 2B annotated close up above, the first edge #1E is closer to the peripheral circuit region #P-Region than the second edge #2E); the first distance from the first edge of the core signal wiring to the contact plug gradually increases as the distance of the contact plug from the peripheral circuit region increases ([0016], figure 2B annotated close up above, the first distance #1D gradually increases as the distance from the contact plug #MC from the peripheral circuit region increases #P-Region (as seen when the right core signal wiring #343-right is compared to the left core signal wiring #343-left)).
Regarding claim 17. Choi as modified discloses wherein a second distance from the second edge of the core signal wiring to the contact plug gradually decreases as the distance of the contact plug from the peripheral circuit region increases ([0016], figure 2B annotated close up above, a second distance #2D from the second edge #2E of the core signal wiring #343-right gradually decreases as the of the contact plug #MC from the peripheral circuit region #P-Region increase (as seen when the right core signal wiring #343-right is compared to the left core signal wiring #343-left)).
Regarding claim 18. Choi as modified discloses wherein a positional relationship between the core circuit wiring and the contact plug is constant regardless of a distance from the peripheral circuit region ([0016], figure 2B annotated above, a positional relationship between the core signal wiring #343bw and the contact plug #MC is constant regardless of the distance from the contact plug #MC to the peripheral circuit region #P-Region).
Claim 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US-20220262721-A1 referred as Choi) in view of Lee et al. (US-20200365706-A1 referred as Lee) and Lee (US-20220199135-A1 referred as Lee #2).
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Regarding claim 19. Choi discloses a semiconductor device, comprising:
a substrate including a cell array region, a core region, and a peripheral circuit region ([0016], figure 2B rotated and annotated above, a substrate #301 includes a cell array region #CA, a core region #PA, and a peripheral circuit region #P-Region2);
an insulation layer positioned on the core circuit wiring ([0016], figure 2B rotated and annotated above, an insulation layer #IL positioned on the core circuit wiring #UM2);
a core signal wiring on the insulation layer ([0016], figure 2B rotated and annotated above, a core signal wiring #343bw on the insulation layer #IL); and
a contact plug penetrating the insulation layer and between the core circuit wiring and the core signal wiring ([0016], figure 2B rotated and annotated above, a contact plug #MC penetrating through the insulation layer #IL and in between the core signal wiring #343bw and the core circuit wiring #UM2), wherein
the contact plug connects the core circuiting wiring to the core signal wiring ([0016], figure 2B rotated and annotated above, a contact plug #MC connects the core signal wiring #343bw and the core circuit wiring #UM2), and
a positional relationship between the core signal wiring and the contact plug is different depending on a distance of the contact plug from the peripheral circuit region ([0016], figure 2B rotated and annotated above, a positional relationship between the core signal wiring $343bw and the contact plug #MC is different depending on the distance of the contact plug #MC to the peripheral circuit region #P-Region (it can be further seen when comparing #343bw-left2 and #343bw-right2)).
Choi lacks a memory cell on the cell array region of the substrate;
a gate stack on the core region of the substrate, the substrate including an impurity region positioned at both sides of the gate stack;
a core circuit wiring connected to the impurity region.
Lee discloses a gate stack on the core region of the substrate, the substrate including an impurity region positioned at both sides of the gate stack ([0053], figure 1B, a gate stack #GS on the core region #A-A of the substrate #101, wherein the substrate #101 includes impurity regions #123 positioned at both sides of the gate stack #GS);
a core circuit wiring connected to the impurity region ([0053], figure 1B, the core circuit wiring #193 is connected to the impurity region #123 as described in [0160]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Choi to include gate stacks and impurity regions as taught by Lee in order to have enhanced channel control, improved device performance, and to increase device versatility.
Choi as modified by Lee still lacks a memory cell on the cell array region of the substrate.
Lee #2 discloses a memory cell on the cell array region of the substrate ([0051], figure 3, a memory cell #ML is on the cell array region #CAR of the substrate #101 as illustrated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Choi as modified by Lee to include a memory cell on the cell array region as taught by Lee #2 in order to have an increased storage density, additional support for advanced architectures, and for flexibility in data types.
Regarding claim 20. Choi as modified discloses
Flipped and Annotated figure 2a
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wherein the core signal wiring comprises a first edge and a second edge opposite each other ([0032], figure 2a above flipped and annotated, the core signal wiring #343bw-left2 comprises a first edge #1E and a second edge #2E opposite of each other);
the first edge is closer to the peripheral circuit region than the second edge ([0032], figure 2a above flipped and annotated, the first edge #1E is closer to the peripheral circuit region #P-Region2 than the second edge #2E); and
a first distance from the first edge of the core signal wiring to the contact plug gradually increases as the distance of the contact plug from the peripheral circuit region increases ([0032], figure 2a above flipped and annotated, a first distance #1D in the core signal wiring #343bw-left2 is gradually increasing when compared to core signal wiring #343bw-right2 as the distance to the peripheral circuit region #P-Region2 increases).
Allowable Subject Matter
Claims 4-10, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Kim et al. (US-20240188293-A1) and Choi et al. (US-20240155831-A1) for teaching the cell array regions, contact plugs, and positional relationships.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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