DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-12 and 14-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. (2024/0339536).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Re claim 1, Choi et al. disclose (Fig. 4) a diode pattern (150/350) on a base insulating layer (290), the diode pattern including a first conductive region (150) and a second conductive region (350) having opposite conductivity types to each other ([0124]); an insulating layer (190) covering the diode pattern on the base insulating layer (290); a wiring portion (196) on the insulating layer (190); and a through connector (170) extending through the insulating layer (190) at a periphery of the diode pattern (150) to electrically connect the diode pattern (150) and the wiring portion (196).
Re claim 2, Choi et al. disclose wherein the through connector includes a first through connector (170) and a second through connector (370), the first through connector (170) connected to the first conductive region (150) at a first side of the diode pattern, the second through connector (370) connected to the second conductive region (350) at a second side of the diode pattern opposite to the first side.
Re claim 3, Choi et al. disclose wherein the first conductive region (150) and the second conductive region (350) are adjacent to each other in a first direction, the first through connector (170) is at the first side of the diode pattern in a second direction, the second direction crossing the first direction, and the second through connector (370) is at the second side of the diode pattern in the second direction.
Re claim 7, Choi et al. disclose wherein a side surface of the diode pattern (150) and a side surface of the through connector (170) are connected to each other.
Re claim 8, Choi et al. disclose wherein a metal-semiconductor compound layer (155) is at a boundary between the side surface of the diode pattern and the side surface of the through connector ([0158] & [0162]).
Re claim 9, Choi et al. disclose wherein the insulating layer (190) includes an upper insulating portion on the diode pattern (Fig. 4).
Re claim 10, Choi et al. disclose wherein the diode pattern (150) and the through connector (170) are spaced apart from each other, and the semiconductor device further comprises a back contact portion (50) extending through at least a portion of the base insulating layer (290) and electrically connecting a back surface of the diode pattern and a back surface of the through connector.
Re claim 11, Choi et al. disclose wherein the first conductive region (150) and the second conductive region (350) are adjacent to each other in a first direction, the through connector includes a first through connector (170) at a first side of the diode pattern in a second direction crossing the first direction, and a second through connector (370) at a second side of the diode pattern opposite to the first side in the second direction, and the back contact portion includes a first back contact portion (50) extending in the second direction and electrically connecting the first conductive region (150) to the first through connector (170), and a second back contact (60) portion extending in the second direction and electrically connecting the second conductive region (370) to the second through connector (370).
Re claim 12, Choi et al. disclose wherein the first back contact portion (50) and the second back contact portion (60) extend in the second direction and are opposite to each other based on the diode pattern.
Rew claim 14, Choi et al. disclose further comprising the insulating layer (190) includes an upper insulating portion on the diode pattern (150).
Re claim 15, Choi et al. disclose a diode pattern on a base insulating layer (290), the diode pattern including a first conductive region (150) and a second conductive region (350) having opposite conductivity types to each other ([0124]); an insulating layer (190) covering the diode pattern (150) on the base insulating layer (290); a wiring portion (196) on the insulating layer (190); and a connector (170) electrically connecting a side surface or a back surface of the diode pattern (150) and the wiring portion (196).
Re claim 16, Choi et al. disclose wherein the connector (170) includes a through connector (170) extending through the insulating layer (190) and connected to a side surface of the diode pattern (150).
Re claim 17, Choi et al. disclose wherein the connector includes a through connector (170) and a back contact portion (50), the through connector spaced apart from the diode pattern (150) and extending through the insulating layer (190), the back contact portion (50) extending through at least a portion of the base insulating layer (290) and electrically connecting the back surface of the diode pattern (150) to a back surface of the through connector (170).
Allowable Subject Matter
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 18, the known prior art does not teach the claim as a whole. In particular, the prior art does not disclose or fairly suggest a second semiconductor device in the second region, the second semiconductor device including a back power distribution network (BSPDN) structure, the BSPDN structure including a back wiring portion, the back wiring porting including a back contact via extending through the base insulating layer, wherein the first semiconductor device includes, a diode pattern on the base insulating layer, the diode pattern including a first conductive region and a second conductive region, the first conductive region and the second conductive region having opposite conductivity types to each other in combination with the remaining limitations called for in claim 18.
None of the prior art on record contains such a limitation, nor given the prior art on record is it obvious to one ordinarily skilled in the art to add said limitations as recited in claim 8. Therefore, claim 18 is allowed as it is not anticipated by or obvious over the teachings of the prior art on record. Furthermore, claims 19 and 20 are also allowed as they depend from an allowed base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 4-6 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Pending the correction of issues outlined in the rejection above, the following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest the following in combination the remaining limitations called for in each claim:
wherein the first conductive region includes a plurality of first conductive regions and the second conductive region includes a plurality of second conductive regions, the plurality of first conductive regions and the plurality of second conductive regions are alternately positioned in a first direction, and the through connector includes a plurality of first through connectors at a first side of the diode pattern in a second direction crossing the first direction and connected to the plurality of first conductive regions, respectively, and a plurality of second through connectors at a second side of the diode pattern opposite to the first side in the second direction and connected to the plurality of second conductive regions, respectively, as recited in claim 4;
wherein the wiring portion includes a first wiring portion extending in the first direction at the first side of the diode pattern and electrically connected to the plurality of first through connectors, and a second wiring portion extending in the first direction at the second side of the diode pattern and electrically connected to the plurality of second through connectors, as recited in claim 5;
wherein the diode pattern, the first wiring portion, and the second wiring portion each has a straight shape extending in the first direction, as recited in claim 6
wherein a metal-semiconductor compound layer is at a boundary between the back surface of the diode pattern and the back contact portion, as recited in claim 13.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0047577 A1, US 2025/0133756 A1, US 2022/0406928 A1 and US 2023/0103191 A1 disclose a similar configuration for a diode type semiconductor device with connectors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE MANDALA whose telephone number is (571)272-1858. The examiner can normally be reached 8:00-5:00 PM.
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 August 3, 2026
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