DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention group I, Species 1, Fig. 6 in the reply filed on 06/22/2026 is acknowledged.
Claims 12-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR10-2023-0111535 filed on 08/24/2023. The foreign application is not in English. The certified copy of the foreign priority application KR10-2023-0111535 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application KR10-2023-0111535 that is not in English, an English translation of the non-English language foreign application KR10-2023-0111535 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Objections
Claim 1 is objected to because of the following informalities: claim 1 recites “a second diodestructure” which appears to be a mistyping of -- a second diode structure--. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Cho et al. (KR20170109118A).
Regarding claim 1, IN et al. discloses in Fig. 1, Fig. 3 a display apparatus comprising:
a first gate line [VGH] configured to receive a first gate voltage;
a second gate line [VGL] configured to receive a second gate voltage;
a first data line [DL1] configured to transfer a first data signal to a first pixel line [PXL];
a second data line [DL2] configured to transfer a second data signal to a second pixel line.
IN et al. fails to disclose
an electrostatic blocking portion including a first electrostatic line and a second electrostatic line,
wherein the first electrostatic line is connected to the first data line by a first diode structure and connected to the second data line by a second diode structure,
the second electrostatic line is connected to the first data line by the first diode structure and is connected to the second data line by the second diode structure, and
the first electrostatic line is electrically separated from the first gate line, and
the second electrostatic line is electrically separated from the second gate line.
Cho et al. discloses in Fig. 1, Fig. 3
an electrostatic blocking portion [EDC] including a first electrostatic line [PL1] and a second electrostatic line [PL2],
wherein the first electrostatic line [PL1] is connected to the first data line [SLj] by a first diode structure and connected to the second data line [SLj+1] by a second diode structure,
the second electrostatic line [PL2] is connected to the first data line [SLj] by the first diode structure and is connected to the second data line [SLj+1] by the second diode structure, and
the first electrostatic line [PL1] is electrically separated from the first gate line [GLi], and
the second electrostatic line [PL2] is electrically separated from the second gate line [GLi+1].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Cho et al. into the method of IN et al. to include an electrostatic blocking portion including a first electrostatic line and a second electrostatic line, wherein the first electrostatic line is connected to the first data line by a first diode structure and connected to the second data line by a second diode structure, the second electrostatic line is connected to the first data line by the first diode structure and is connected to the second data line by the second diode structure, and the first electrostatic line is electrically separated from the first gate line, and the second electrostatic line is electrically separated from the second gate line. The ordinary artisan would have been motivated to modify IN et al. in the above manner for the purpose of providing a display device having an electrostatic discharge circuit so that it can protect an internal circuit from a discharger by rapidly discharging static electricity introduced from the outside. In addition, open short tests can be performed on the signal lines, if the signal lines are incorrectly formed, they can be easily repaired [paragraph [0001]-[0002], [0025] of Cho et al.].
Regarding claim 2, IN et al. discloses in Fig. 1, Fig. 3, paragraph [0088],
wherein the first gate voltage [VGH] is a gate high-level voltage, and the second gate voltage [VGL] is a gate low-level voltage.
Regarding claims 3-6, IN et al. discloses in Fig. 1-Fig. 3, paragraph [0053]-[0056]
wherein the first gate line [GPL/VGH] is connected to a 1-1 pad [one of PAD_G];
a first power line [PL/PL1] is connected to a 1-2 pad [one of PAD_P], and the 1-2 pad [one of PAD_P] is apart from the 1-1 pad [PAD_G];
wherein the 1-1 pad [one of PAD_G] and the 1-2 pad [one of PAD_P] are electrically separated from each other;
wherein the second gate line [GPL/VGL] is connected to a 2-1 pad [second one of PAD_G],
a second power line [PL/PL2] is connected to a 2-2 pad [second one of PAD_P], and the 2-2 pad [second one of PAD_P] is apart from the 2-1 pad [second one of PAD_G];
wherein the 2-1 pad [second one of PAD_G] and the 2-2 pad [second one of PAD_P] are electrically separated from each other.
Cho et al. discloses the first power line is the first electrostatic line PL1 and the second power line is the second electrostatic line PL2
Thus, the combination of IN et al. and Cho et al. would result to “the first electrostatic line is connected to a 1-2 pad, and the 1-2 pad is apart from the 1-1 pad; wherein the 1-1 pad and the 1-2 pad are electrically separated from each other; wherein the second gate line is connected to a 2-1 pad, the second electrostatic line is connected to a 2-2 pad, and the 2-2 pad is apart from the 2-1 pad.”
Regarding claim 7, IN et al. further discloses in paragraph [0003], [0010], [0049]
a data driver [DDV] configured to generate the first data signal and the second data signal.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20140167769) in view of Cho et al. (KR20170109118A).
Regarding claim 1, Kim et al. discloses in Fig. 2B, Fig. 5 a display apparatus comprising:
a first gate line [VGH] configured to receive a first gate voltage;
a second gate line [VGL] configured to receive a second gate voltage;
a first data line [DL1] configured to transfer a first data signal to a first pixel line [PXL];
a second data line [DL2] configured to transfer a second data signal to a second pixel line.
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Kim et al. fails to disclose
an electrostatic blocking portion including a first electrostatic line and a second electrostatic line,
wherein the first electrostatic line is connected to the first data line by a first diode structure and connected to the second data line by a second diode structure,
the second electrostatic line is connected to the first data line by the first diode structure and is connected to the second data line by the second diode structure, and
the first electrostatic line is electrically separated from the first gate line, and
the second electrostatic line is electrically separated from the second gate line.
Cho et al. discloses in Fig. 1, Fig. 3
an electrostatic blocking portion [EDC] including a first electrostatic line [PL1] and a second electrostatic line [PL2],
wherein the first electrostatic line [PL1] is connected to the first data line [SLj] by a first diode structure and connected to the second data line [SLj+1] by a second diode structure,
the second electrostatic line [PL2] is connected to the first data line [SLj] by the first diode structure and is connected to the second data line [SLj+1] by the second diode structure, and
the first electrostatic line [PL1] is electrically separated from the first gate line [GLi], and
the second electrostatic line [PL2] is electrically separated from the second gate line [GLi+1].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Cho et al. into the method of Kim et al. to include an electrostatic blocking portion including a first electrostatic line and a second electrostatic line, wherein the first electrostatic line is connected to the first data line by a first diode structure and connected to the second data line by a second diode structure, the second electrostatic line is connected to the first data line by the first diode structure and is connected to the second data line by the second diode structure, and the first electrostatic line is electrically separated from the first gate line, and the second electrostatic line is electrically separated from the second gate line. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing a display device having an electrostatic discharge circuit so that it can protect an internal circuit from a discharger by rapidly discharging static electricity introduced from the outside. In addition, open short tests can be performed on the signal lines, if the signal lines are incorrectly formed, they can be easily repaired [paragraph [0001]-[0002], [0025] of Cho et al.].
Regarding claim 2, Kim et al. discloses in Fig. 2A, 2B, paragraph [0057],
wherein the first gate voltage [VGH] is a gate high-level voltage, and the second gate voltage [VGL] is a gate low-level voltage.
Claims 3-9, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20140167769) in view of Cho et al. (KR20170109118A) as applied to claim 2 above and further in view of IN et al. (US Pub. 20230206833).
Regarding claims 3-6, Kim et al. discloses in Fig. 2B, Fig. 5
wherein the first gate line [VGH] is connected to a 1-1 pad;
wherein the second gate line [VGL] is connected to a 2-1 pad.
Kim et al. and Cho et al. fails to disclose
the first electrostatic line is connected to a 1-2 pad, and the 1-2 pad is apart from the 1-1 pad;
wherein the 1-1 pad and the 1-2 pad are electrically separated from each other;
wherein the second gate line is connected to a 2-1 pad, the second electrostatic line is connected to a 2-2 pad, and the 2-2 pad is apart from the 2-1 pad.
IN et al. discloses in Fig. 1-Fig. 3, paragraph [0053]-[0056]
a first power line [PL/PL1] is connected to a 1-2 pad [one of PAD_P], and the 1-2 pad [one of PAD_P] is apart from the 1-1 pad [one of PAD_G];
wherein the 1-1 pad [one of PAD_G] and the 1-2 pad [one of PAD_P] are electrically separated from each other;
a second power line [PL/PL2] is connected to a 2-2 pad [second one of PAD_P], and the 2-2 pad [second one of PAD_P] is apart from the 2-1 pad [second one of PAD_G];
wherein the 2-1 pad [second one of PAD_G] and the 2-2 pad [second one of PAD_P] are electrically separated from each other.
Cho et al. discloses the first power line is the first electrostatic line PL1 and the second power line is the second electrostatic line PL2
Thus, the combination of IN et al. and Cho et al. would result to “the first electrostatic line is connected to a 1-2 pad, and the 1-2 pad is apart from the 1-1 pad; wherein the 1-1 pad and the 1-2 pad are electrically separated from each other; wherein the second gate line is connected to a 2-1 pad, the second electrostatic line is connected to a 2-2 pad, and the 2-2 pad is apart from the 2-1 pad.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of IN et al. and Cho et al. into the method of Kim et al. to include the first electrostatic line is connected to a 1-2 pad, and the 1-2 pad is apart from the 1-1 pad; wherein the 1-1 pad and the 1-2 pad are electrically separated from each other; wherein the second gate line is connected to a 2-1 pad, the second electrostatic line is connected to a 2-2 pad, and the 2-2 pad is apart from the 2-1 pad. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing pads for transferring a gate power voltage to first and second gate power lines and transferring power voltages to first and second power lines [paragraph [0054], [0056] of IN et al.].
Regarding claim 7, Kim et al. discloses in Fig. 2A-2B, paragraph [0055]
a data driver [260] configured to generate the first data signal and the second data signal.
IN et al. also discloses in paragraph [0003], [0010], [0049]
a data driver [DDV] configured to generate the first data signal and the second data signal.
Regarding claims 8-9, Kim et al. discloses in Fig. 2B, Fig. 5
a first connection member [TT1] connecting the 1-1 pad to the first data line [DL1] and to the data driver [260];
a second connection member [TT2] connecting the 2-1pad to the second data line [DL2] and to the data driver [260].
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IN et al. discloses in Fig. 1 and paragraph [0055]
a 1-3 pad [one of PAD_D] electrically connected to the first data line [DL1] and to the data driver [DDV];
a 2-3 pad [second one of PAD_D] electrically connected to the second data line [DL2] and to the data driver [DDV].
Consequently, the combination of Kim et al. and IN et al. result to “a 1-3 pad electrically connected to the data driver; and a first connection member connecting the 1-1 pad to the 1-3 pad; a 2-3 pad electrically connected to the data driver; and a second connection member connecting the 2-1 pad to the 2-3 pad.”
Regarding claim 11, Cho et al. discloses in Fig. 1 wherein the electrostatic blocking portion [140] is arranged between a display area [110] in which at least one pixel [PX] is arranged, and the data driver [120] in a plan view.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20140167769) in view of Cho et al. (KR20170109118A), and IN et al. (US Pub. 20230206833) as applied to claim 9 above and further in view of Jun (US Pub. 20200218395) and Dong et al. (US Pub. 20160313392).
Regarding claim 10, Kim et al. fails to disclose
a printed circuit board including the first connection member and the second connection member, wherein the printed circuit board is attached to the 1-1 pad, the 1-2 pad, the 1-3 pad, the 2-1 pad, the 2-2 pad, and the 2-3 pad.
Kim et al. discloses in Fig. 2B, Fig. 5
a test circuit including the first connection member and the second connection member.
Jun discloses in Fig. 4, paragraph [0067]
the printed circuit board [FPC-300] is attached to the 1-1 pad, the 1-2 pad, the 1-3 pad, the 2-1 pad, the 2-2 pad, and the 2-3 pad [300_PD].
Dong et al. discloses in Fig. 1, Fig. 2, paragraph [0009]-[0017]
a printed circuit board [3] including a test circuit, wherein the printed circuit board [3] is attached to pads.
The combination of Jun, Dong et al. and Kim et al. would result to “a printed circuit board including the first connection member and the second connection member.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jun and Dong et al. into the method of Kim et al. to include a printed circuit board including the first connection member and the second connection member, wherein the printed circuit board is attached to the 1-1 pad, the 1-2 pad, the 1-3 pad, the 2-1 pad, the 2-2 pad, and the 2-3 pad. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable method to form a display device including test circuit while preventing pads from contacting the outside and preventing corrosion of pads and signal abnormity in signal lines resulting therefrom during testing [paragraph [0015] of Dong et al.].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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